ST10F296 datasheet(211/346 Pages) STMICROELECTRONICS

номер детали	ST10F296

подробное описание детали	High performance 16-bit CPU with DSP functions

PDF	346 Pages

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производитель	STMICROELECTRONICS [STMicroelectronics]

домашняя страница	http://www.st.com

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ST10F296E

Watchdog timer

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Watchdog timer

The watchdog timer is a fail-safe mechanism which prevents the microcontroller from

malfunctioning over long periods of time.

The watchdog timer is always enabled after a reset of the chip and can only be disabled in

the time interval until the EINIT (end of initialization) instruction has been executed.

Therefore, the chip start-up procedure is always monitored. Software must be designed to

service the watchdog timer before it overflows. If, due to hardware or software related

failures, the software fails to do so, the watchdog timer overflows and generates an internal

hardware reset. It pulls the RSTOUT pin low to allow external hardware components to be

reset.

Each of the different reset sources is indicated in the watchdog control register (WDTCON).

The bits indicated in Table 127 are cleared with the EINIT instruction. The source of the

reset can be identified during the initialization phase.

Watchdog control register (WDTCON)

WDTCON (FFAEh/D7h)

SFR

Reset value: 00xxh

987

65432

WDTREL

TIN

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ST10F296 датащи(PDF) 211 Page - STMicroelectronics