SPC563M64L7 datasheet(37/48 Pages) STMICROELECTRONICS

37 / 48 page

SPC563Mxx

Device overview

Doc ID 13850 Rev 6

37/48

The FlexCAN module provides the following features:

●

Full Implementation of the CAN protocol specification, Version 2.0B

–

Standard data and remote frames

–

Extended data and remote frames

–

Zero to eight bytes data length

–

Programmable bit rate up to 1 Mbit/s

●

Content-related addressing

●

64 / 32 message buffers of zero to eight bytes data length

●

Individual Rx Mask Register per message buffer

●

Each message buffer configurable as Rx or Tx, all supporting standard and extended

messages

●

Includes 1056 / 544 bytes of embedded memory for message buffer storage

●

Includes a 256-byte and a 128-byte memories for storing individual Rx mask registers

●

Full featured Rx FIFO with storage capacity for six frames and internal pointer handling

●

Powerful Rx FIFO ID filtering, capable of matching incoming IDs against 8 extended, 16

standard or 32 partial (8 bits) IDs, with individual masking capability

●

Selectable backwards compatibility with previous FlexCAN versions

●

Programmable clock source to the CAN Protocol Interface, either system clock or

oscillator clock

●

Listen only mode capability

●

Programmable loop-back mode supporting self-test operation

●

3 programmable Mask Registers

●

Programmable transmit-first scheme: lowest ID, lowest buffer number or highest priority

●

Time Stamp based on 16-bit free-running timer

●

Global network time, synchronized by a specific message

●

Maskable interrupts

●

Warning interrupts when the Rx and Tx Error Counters reach 96

●

Independent of the transmission medium (an external transceiver is assumed)

●

Multi master concept

●

High immunity to EMI

●

Short latency time due to an arbitration scheme for high-priority messages

●

Low power mode, with programmable wake-up on bus activity

3.3.18

System timers

The system timers provide two distinct types of system timer:

●

Periodic interrupts/triggers using the Peripheral Interrupt Timer (PIT)

●

Operating system task monitors using the System Timer Module (STM)

Peripheral Interrupt Timer (PIT)

The PIT provides five independent timer channels, capable of producing periodic interrupts

and periodic triggers. The PIT has no external input or output pins and is intended to be

used to provide system ‘tick’ signals to the operating system, as well as periodic triggers for

eQADC queues. Of the five channels in the PIT, four are clocked by the system clock, one is

SPC563M64L7 датащи(PDF) 37 Page - STMicroelectronics

SPC563M64L7 датащи(HTML) 37 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

датащи скачать

ссылки URL