SPC563M64L7 datasheet(20/48 Pages) STMICROELECTRONICS

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Device overview

SPC563Mxx

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Doc ID 13850 Rev 6

storage model for single-precision floating-point data types of 32 bits and the normal integer

type. Single-cycle floating-point add, subtract, multiply, compare, and conversion operations

are provided. Divide instructions are multi-cycle and are not pipelined.

The Signal Processing Extension (SPE) Auxiliary Processing Unit (APU) provides hardware

SIMD operations and supports a full complement of dual integer arithmetic operation

including Multiply Accumulate (MAC) and dual integer multiply (MUL) in a pipelined fashion.

The general purpose register file is enhanced such that all 32 of the GPRs are extended to

64 bits wide and are used for source and destination operands, thus there is a unified

storage model for 32

×32 MAC operations which generate greater than 32-bit results.

The majority of both scalar and vector operations (including MAC and MUL) are executed in

a single clock cycle. Both scalar and vector divides take multiple clocks. The SPE APU also

provides extended load and store operations to support the transfer of data to and from the

extended 64-bit GPRs.

The CPU includes support for Variable Length Encoding (VLE) instruction enhancements.

This enables the classic Power Architecture instruction set to be represented by a modified

instruction set made up from a mixture of 16- and 32-bit instructions. This results in a

significantly smaller code size footprint without noticeably affecting performance. The Power

Architecture instruction set and VLE instruction set are available concurrently. Regions of

the memory map are designated as PPC or VLE using an additional configuration bit in

each of Table Look-aside Buffers (TLB) entries in the MMU.

The CPU core is enhanced by the addition of two additional interrupt sources; Non-

Maskable Interrupt and Critical Interrupt. These two sources are routed directly from

package pins, via edge detection logic in the SIU to the CPU, bypassing completely the

Interrupt Controller. Once the edge detection logic is programmed, it cannot be disabled,

except by reset. The non-maskable Interrupt is, as the name suggests, completely un-

maskable and when asserted will always result in the immediate execution of the respective

interrupt service routine. The non-maskable interrupt is not guaranteed to be recoverable.

The Critical Interrupt is very similar to the non-maskable interrupt, but it can be masked by

other exceptional interrupts in the CPU and is guaranteed to be recoverable (code execution

may be resumed from where it stopped).

The CPU core has an additional ‘Wait for Interrupt’ instruction that is used in conjunction

with low power STOP mode. When Low Power Stop mode is selected, this instruction is

executed to allow the system clock to be stopped. An external interrupt source or the system

wake-up timer is used to restart the system clock and allow the CPU to service the interrupt.

3.3.2

Crossbar

The XBAR multi-port crossbar switch supports simultaneous connections between three

master ports and four slave ports. The crossbar supports a 32-bit address bus width and a

64-bit data bus width.

The crossbar allows three concurrent transactions to occur from the master ports to any

slave port; but each master must access a different slave. If a slave port is simultaneously

requested by more than one master port, arbitration logic selects the higher priority master

and grants it ownership of the slave port. All other masters requesting that slave port are

stalled until the higher priority master completes its transactions. Requesting masters are

treated with equal priority and are granted access to a slave port in round-robin fashion,

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