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SPC563M64L7 датащи(PDF) 13 Page - STMicroelectronics |
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SPC563M64L7 датащи(HTML) 13 Page - STMicroelectronics |
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13 / 48 page ![]() SPC563Mxx Device overview Doc ID 13850 Rev 6 13/48 – Configurable bus speed modes –Bus monitor – Configurable wait states ● System integration unit (SIU) – Centralized GPIO control of 80 I/O pins – Centralized pad control on a per-pin basis Pin function selection Configurable weak pull-up or pull-down Drive strength Slew rate Hysteresis – System reset monitoring and generation – External interrupt inputs, filtering and control – Critical Interrupt control – Non-Maskable Interrupt control – Internal multiplexer subblock (IMUX) Allows flexible selection of eQADC trigger inputs (eTPU, eMIOS and external signals) Allows selection of interrupt requests between external pins and DSPI ● Error correction status module (ECSM) – Configurable error-correcting codes (ECC) reporting – Single-bit error correction reporting ● On-chip Flash memory – Up to 1.5 MB flash memory, accessed via a 64-bit wide bus interface – 16 KB shadow block – Fetch Accelerator Provide single cycle flash access at 80 MHz Quadruple 128-bit wide prefetch/burst buffers Prefetch buffers can be configured to prefetch code or data or both – Censorship protection scheme to prevent flash content visibility – Flash divided into two independent arrays, allowing reading from one array while erasing/programming the other array (used for EEPROM emulation) – Memory block: For SPC563M64: 18 blocks (4 × 16 KB, 2 × 32 KB, 2 × 64 KB, 10 × 128 KB) For SPC563M60P: 14 blocks (4 × 16 KB, 2 × 32 KB, 2 × 64 KB, 6 × 128 KB) For SPC563M54P: 12 blocks (4 × 16 KB, 2 × 32 KB, 2 × 64 KB, 4 × 128 KB) – Hardware programming state machine ● On-chip static RAM – For SPC563M64: 94 KB general purpose RAM of which 32 KB are on standby power supply – For SPC563M60P: 64 KB general purpose RAM of which 32 KB are on standby power supply – For SPC563M54P: 48 KB general purpose RAM of which 24 KB are on standby |
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