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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LQFP100 датащи(PDF) 62 Page - STMicroelectronics |
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LQFP100 датащи(HTML) 62 Page - STMicroelectronics |
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62 / 116 page  Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x 62/116 DocID14619 Rev 13 Figure 10. VDD_HV and VDD_BV maximum slope When STANDBY mode is used, further constraints are applied to the both VDD_HV and VDD_BV in order to guarantee correct regulator function during STANDBY exit. This is described on Figure 11. STANDBY regulator constraints should normally be guaranteed by implementing equivalent of CSTDBY capacitance on application board (capacitance and ESR typical values), but would actually depend on exact characteristics of application external regulator. Figure 11. VDD_HV and VDD_BV supply constraints during STANDBY mode exit VDD_HV t d d VDD POWER UP POWER DOWN VDD_HV(MAX) FUNCTIONAL RANGE VPORH(MAX) VDD_HV VDD_HV(MIN) VDD(STDBY) VDD_HV VDD_HV(MAX) VDD_LV t d d VDD STDBY t d d VDD STDBY VDD(STDBY) VDD_LV(NOMINAL) 0V |
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