L99MC6GJ datasheet(29/55 Pages) STMICROELECTRONICS

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L99MC6GJ

Functional description of the SPI

8.2

SPI communication flow

8.2.1

General description

The proposed SPI communication is based on a standard SPI interface structure using CSN

(chip select not), SDI (serial data in), SDO (serial data out/error) and SCK (serial clock)

signal lines.

At the beginning of each communication the master reads the <SPI-frame-ID> register

(ROM address 3EH) of the slave device. This 8-bit register indicates the SPI frame length

(16 bit for the L99MC6GJ) and the availability of additional features.

Each communication frame consists of an instruction byte which is followed by 1 data byte

(see Figure 12).

The data returned on SDO within the same frame always starts with the <Global Status>

is ‘In-frame-response’, see Figure 12).

For Write cycles the <Global Status> register is followed by the previous content of the

addressed register.

For Read cycles the <Global Status> register is followed by the content of the addressed

8.2.2

Command byte

Each communication frame starts with a command byte. It consists of an operating code

which specifies the type of operation (<Read>, <Write>, <Read and Clear Status>, <Read

Device Information>) and a 6-bit address.

Table 12. Command byte - general description

MSB

LSB

Operating code

Address

OC1

OC0

Table 13. Data byte - general description

MSB

LSB

Bit7

Bit6

Bit5

Bi4

Bit3

Bit2

Bit1

Bit0

Table 14. Command byte

MSB

LSB

Operating code

Address

OC1

OC0

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