L99MM70XP datasheet(52/68 Pages) STMICROELECTRONICS

52 / 68 page

SPI control and status registers

L99MM70XP

52/68

Doc ID 022637 Rev 2

The <Write Mode> and <Read Mode> operations allow access to the RAM of the device.

A <Read and Clear Mode> operation is used to read a status register and subsequently

clear its content.

The <Read Device Information> allows access to the ROM area which contains device

related information such as <ID-Header>, <Product Code>, <Silicon Version> and <SPI-

frame-ID>.

9.1.4

Global status byte

Table 29.

Global status byte

Bit

Global status byte

Name

GL_ER

CO_ER

NRECE

TSD

TW_OL

UV_OV_OC

VCC_FAIL

PASSIVE

Reset

GL_ER

Global error flag.

Failures of Bits 0-6 are always linked to the global error flag. This flag is generated by an OR

combination of all failure events of the device. If the TW_OL_MSK bit is set in the configuration

GL_ER is reflected via the DO pin while CSN is held low and no clock signal is available. The flag

remains as long as CSN is low. This operation does not cause the communication error bit in the

<Global status byte> to be set.

CO_ER

Communication error.

If the number of clock pulses within the previous frame is not 24, the frame is ignored, and this bit

is set.

CO_ER is not set, if CSN is held low without any clock to check the GL_ER bit.

NRECE = NOT

(C_RESET OR

CO_ER)

Chip reset (C_RESET) = Registers have been set to default.

After power on NRECE is ‘0’ and is set to ‘1’ by a valid SPI communication.

NRECE is also ‘0’ if there was a communication error or if there was a reset due to stuck-at-0 or

stuck-at-1 at the SPIDI input.

When NRECE is active (‘0’), the gate drivers are switched off (resistive path to source). The gate

drivers can only be activated after NRECE has been reset with an SPI command.

TSD

Thermal shut down due to an internal sensor. All the gate drivers and the charge pump are

switched off (resistive path to source). The TSD bit has to be cleared through a software reset to

reactivate the gate drivers and the charge pump.

TW_OL

Thermal warning OR open-load.

UV_OV_OC

Under voltage OR overvoltage OR overcurrent

VCC_FAIL

VCC fail

PASSIVE

Device in passive mode.

This bit is set if the device enters passive mode (due to watchdog failure, VCC under voltage,

thermal shutdown TSD2 or SPI data in stuck at 0 or 1)

The bit is reset when the micro sends the first correct SPI frame after entering passive mode.

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