PC87364-XXXSLASHVLA datasheet(26/180 Pages) NSC

26 / 180 page

1.0 Signal/Pin Connection and Description (Continued)

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1.4.13

Strap Configuration

1.4.14

System Wake-Up Control

Signal

Pin/s

I/O Buffer Type Power Well

Description

BADDR

101

INSTRP

VDD

Base Address. Sampled by the trailing edge of the system reset

to determine the base address of the conﬁguration Index-Data

resistor.

If no pull-up resistor is connected, it is sampled low, setting the

Index-Data pair at 2Eh-2Fh.

Connecting a 10K external pull-up resistor to VDD would make it

sample high, setting the Index-Data pair at 4Eh-4Fh.

PSLDC0

PSLDC1

107

INSTRP

VSB

Note 1.

Note 1.Make sure that the Serial Port driver is back-drive protected.

Power Supply and LED Conﬁguration. If no pull-up resistor is

connected to these pins, pins 33-35 and 37 function as

PWBTOUT, PSON, PWBTIN and SLPS5 respectively.

Connecting a 10K external pull-up resistor to VSB causes these

pins to function as GPOS0, GPOS1, GPIS2, respectively.

PSONPOL

109

INSTRP

VSB

Note 1.

Power Supply On Polarity. If no pull-up resistor is connected to

this pin, PSON is set active low with open-drain output.

Connecting a 10K external pull-up resistor to VSB causes PSON

to be set to active high with push-pull output.

TEST

INSTRP

VDD

Test. If sampled high on the trailing edge of system reset, this

signal forces the device into test mode. This pin is for National

Semiconductor use only, and should be left unconnected.

Signal

Pin/s

I/O Buffer Type Power Well

Description

LED1

LED2

O12/12

VSB

LED. VSB-powered pins with programmable outputs, each of

which can be used to produce a 0, 0.25, 0.5, 1, 4 Hz waveform for

LED control.

GPIE6-7

58-59

INTS

VSB

General-Purpose Input Event

GPIOE0-5

23-28

I/O

INTS/

OD6,O3/6

VSB

General-Purpose I/O Event. VSB-powered pins.

GPIS2-3

35-36

INTS

VSB

General-Purpose Input Standby. VSB-powered pins.

GPOS0-1

33-34

OD6,O3/6

VSB

General-Purpose Output Standby. VSB-powered pins.

PSON

O4,OD12

VSB

Power Supply On. Active level (low or high via PSONPOL strap)

instructs the main power supply to turn the power on. PSON

output signal is open-drain when active low and push-pull when

active high.

PWBTIN

INTS

VSB

Power Button In. Active (low) level indicates a user request to

turn the power on or off. This pin has an internal Schmidt-trigger

input buffer and debouce protection of at least 16 mS.

PWBTOUT 33

OD12

VSB

Power Button Out. Active (low) level serves as output to the

chipset power button input.

PWUREQ

OD6

VSB

Power-Up Request. Active (low) level indicates that wake-up

event has occurred, and causes the chipset to turn the power

supply on, or to exit its current sleep state. The open-drain output

must be pulled up to VSB in order to function during power-off.

PC87364-XXX/VLA датащи(PDF) 26 Page - National Semiconductor (TI)

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