PC87360 datasheet(76/168 Pages) NSC

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3.0 System Wake-Up Control (SWC) (Continued)

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3.4

SWC REGISTERS

The SWC registers are organized in four banks, all of which are battery-backed. The offsets are related to a base address

that is determined by the SWC Base Address register in the device configuration registers. The lower 19 offsets are common

to the four banks, while the upper offsets (13-1fh) are divided as follows:

Bank 0 holds the Keyboard/Mouse Control registers.

Bank 1 holds the CEIR Control registers.

Bank 2 holds the Event Routing Conﬁguration and Wake-Up Extension Control registers.

Bank 3 holds the Standby General-Purpose I/O (GPIO) Pins Conﬁguration registers.

The active bank is selected through the Configuration Bank Select field (bits 1-0) in the Wake-Up Configuration register

(WK_CFG). See Section 3.4.6.

As a programming aid, the registers are described in this chapter according to the following functional groupings:

General status, enable, conﬁguration and routing registers

Extension enable registers

PS/2 event conﬁguration registers

CEIR event conﬁguration registers

Standby GPIO conﬁguration and control registers

The following abbreviations are used to indicate the Register Type:

R/W = Read/Write

R = Read from a speciﬁc address returns the value of a speciﬁc register. Write to the same address is to a different

W=Write

RO = Read Only

R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

3.4.1

SWC Register Map

The following tables list the SWC registers. For the SWC register bitmap, see Section 3.5.

Table 33. Banks 0, 1, 2 and 3 - The Common Control and Status Register Map

Table 34. Bank 0 - PS/2 Keyboard/Mouse Wake-Up Conﬁguration and Control Register Map

Offset

Mnemonic

Type

Section

00h

WK_STS0

Wake-Up Events Status 0

R/W1C

3.4.2

01h

WK_STS1

Wake-Up Events Status 1

R/W1C

3.4.3

02h

WK_EN0

Wake-Up Enable 0

R/W

3.4.4

03h

WK_EN1

Wake-Up Enable 1

R/W

3.4.5

04h

WK_CFG

Wake-Up Conﬁguration

R/W

3.4.6

05h-07h

Reserved

08h

SB_GPDO0

Standby GPIOE/GPIE Data Out 0

R/W

3.4.31

09h

SB_GPDI0

Standby GPIOE/GPIE Data In 0

3.4.32

0Ah-12h

Reserved

Offset

Mnemonic

Type

Section

13h

PS2CTL

PS/2 Protocol Control

R/W

3.4.16

14h-15h

Reserved

16h

KDSR

Keyboard Data Shift

3.4.17

17h

MDSR

Mouse Data Shift

3.4.18

08h-1Fh

PS2KEY0-PS2KEY7 PS/2 Keyboard Key Data

R/W

3.4.19

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