PC87360 datasheet(75/168 Pages) NSC

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3.0 System Wake-Up Control (SWC) (Continued)

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3.3.4

CEIR Address

A CEIR transmission received on an IRRX pin in a pre-selected standard (NEC, RCA or RC-5) is matched against a pro-

grammable CEIR address. Detection of matching can be used as a wake-up event.

Whenever an IR signal is detected, the receiver immediately enters the active state. When this happens, the receiver keeps

sampling the IR input signal and generates a bit string where a logic 1 indicates an idle condition and a logic 0 indicates the

presence of IR energy. The received bit string is de-serialized and assembled into 8-bit characters.

The expected CEIR protocol of the received signal should be configured through bits 5,4 at the CEIR Wake-Up Control reg-

ister (see Section 3.4.20).

The CEIR Wake-Up Address register (IRWAD) holds the unique address to be compared with the address contained in the

incoming CEIR message. If CEIR is enabled (bit 0 of the IRWCR register is 1) and an address match occurs, then the CEIR

Event Status bit of the WK_STS0 register is set to 1 (see Section 3.4.2).

The CEIR Address Shift register holds the received address which is compared with the address contained in the IRWAD.

The comparison is affected also by the CEIR Wake-Up Address Mask register (IRWAM) in which each bit determines wheth-

er to ignore the corresponding bit in the IRWAD.

If CEIR routing to interrupt request is enabled, the assigned SWC interrupt request may be used to indicate that a complete

address has been received. To get this interrupt when the address is completely received, the IRWAM should be written with

FFh. Once the interrupt is received, the value of the address can be read from the ADSR register.

Another parameter that is used to determine whether a CEIR signal is to be considered valid is the bit cell time width. There

are four time ranges for the different protocols and carrier frequencies. Four pairs of registers define the low and high limits

of each time range. (See Sections 3.4.27 through for more details regarding the recommended values for each protocol.)

The CEIR address detection operates independently of the serial port with the IR (which is powered down with the rest of

the system).

3.3.5

Standby General-Purpose Input Events

A general-purpose event is defined as the detection of falling edge, rising edge, low level or high level on a specific signal.

Each signal’s event is configurable via software. GPIOE0-5 and GPIE6-7 may trigger a system notification by any of the

means mentioned in Section 3.1.

A debouncer of 16 ms is enabled (default) on each event. It may be disabled by software.

3.3.6

GPIO-Triggered Events

A GPIO-triggered event is defined as the detection of falling edge, rising edge, low level or high level on a specific GPIO

signal whose status bit is routed to PWUREQ. Each signal’s event is configurable via software in the GPIO logical device

configuration registers. GPIO00-07, GPIO10-14, GPIO16-17 and GPIO40-47 may trigger a system notification only by

PWUREQ. Other means of system notiﬁcation triggered by GPIOs are available via the GPIO logical device conﬁguration

registers.

A debouncer of 16 ms is enabled (default) on each event. It may be disabled by software.

All GPIO pins are powered by VDD, and therefore can cause an assertion of PWUREQ only when VDD is present.

3.3.7

Software Event

A software event is defined as writing 1 to the Software Event Status bit of the WK_STS0 register. Once this bit is set to 1,

it has the same effect as any other Event Status bit.

Since WK_STS0 is accessible only when VDD is present, the Software Event can be activated only when VDD is present.

3.3.8

Module IRQ Wake-Up Event

A module IRQ wake-up event is defined as the leading edge of the IRQ assertion of any of the following logical devices:

FDC, Parallel Port, Serial Ports 1 and 2, Mouse, KBC, ACB and Fan Speed Control and Monitor (FSCM).

To enable the IRQ of a specific logical device to trigger a wake-up event, the associated Enable bit must be set to 1. This

is bit 4 of the Interrupt Number and Wake-Up on IRQ Enable register, located at index 70h in the configuration space of the

logical device (see Table 10 in

Device Architecture and Configuration chapter). When this bit is set, any IRQ assertion of the

corresponding logical device activates the module IRQ wake-up event. Therefore, the module IRQ wake-up event is a com-

bination of all IRQ signals of the logical devices for which wake-up on IRQ is enabled.

When the event is detected as active, its associated Status bit (bit 7 of the WK0_STS register) is set to 1. If the associated

Enable bit (bit 7 of the WK_EN0 register) is also set to 1, the PWUREQ output is asserted. It remains asserted until the

Status bit is cleared.

Since all the logical devices listed above are powered by VDD, a module IRQ event can be activated only when VDD is

present.

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