PC87332 datasheet(11/98 Pages) NSC

11 / 98 page

10 Pin Description (Continued)

Symbol

Function

DSKCHG

Normal

Disk Change

This input indicates if the drive door has been opened The state of this pin is available

from the Digital Input register This pin can also be configured as the Read Gate (RGATE) data

Mode

separator diagnostic input via the Mode command (see Section 426)

DSKCHG

PPM

Disk Change

This pin provides an additional Disk Change signal in PPM Mode when PNF e 0 (See

PD4 and Table 7-5 for further information)

Mode

DSR12

76 68

Data Set Ready

When low this signal indicates that the data set or MODEM is ready to establish a

communications link The DSR signal is a MODEM status input whose condition the CPU can test by

reading bit 5 (DSR) of the MODEM Status Register (MSR) for the appropriate channel Bit 5 is the

complement of the DSR signal Bit 1 (DDSR) of the MSR indicates whether the DSR input has changed

states since the previous reading of the MSR (See IRRX for further information)

Note

Whenever the DDSR bit of the MSR is set an interrupt is generated If MODEM Status interrupts are enabled

DSTRB

Data Strobe

This signal is used in EPP mode as a data strobe It is active low (See AFD and Table 7-5

for further information)

DTR12

71 63

Data Terminal Ready

When low this output indicates to the MODEM or data set that the UART is

ready to establish a communications link The DTR signal can be set to an active low by programming

bit 0 (DTR) of the MODEM Control Register to a high level A Master Reset operation sets this signal to

its inactive (high) state Loop mode operation holds this signal to its inactive state (See CFG4 – 0 for

further information)

ERR

Error

A connected printer sets this input low when it has detected an error This pin has a nominal 25

kX pull-up resistor attached to it (See HDSEL and Table 7-5 for further information)

FDACK

DMA Acknowledge

Active low input to acknowledge the FDC DMA request and enable the RD and

WR inputs during a DMA transfer When in PC-AT or Model 30 mode this signal is enabled by bit D3

of the Digital Output Register (DOR) When in PS2 mode FDACK is always enabled and bit D3 of the

DOR is reserved FDACK should be held high during IO accesses

FDRQ

DMA Request

Active high output to signal the DMA controller that a FDC data transfer is needed

When in PC-AT or Model 30 mode this signal is enabled by bit D3 of the DOR When in PS2 mode

FDRQ is always enabled and bit D3 of the DOR is reserved

HCS0

Hard Drive Chip Select 0

This output is active in the AT mode when 1) the hard drive registers from

1F0 – 1F7h are selected and the primary address is used or 2) the hard drive registers from 170 – 177h

are selected and the secondary address is used This output is inactive if the IDE interface is disabled

via the Configuration Register (See BADDR1 for further information)

HCS1

Hard Drive Chip Select 1

This output is active in the AT mode when 1) the hard drive registers from

3F6 – 7 are selected and the primary address is used or 2) the hard drive registers from 376 – 377 are

selected and the secondary address is used This output is also inactive if the IDE interface is disabled

via the Configuration Register (See CLK48 for further information)

HDSEL

Normal

Head Select

This output determines which side of the FDD is accessed When active the head

selects side 1 When inactive the head selects side 0

Mode

HDSEL

PPM

Head Select

This pin provides an additional Head Select signal in PPM Mode when PNF e 0 (See

ERR and Table 7-5 for further information)

Mode

IDED7

IDE Bit 7

This pin provides the data bus bit 7 signal to the IDE hard drive during accesses in the

address range 1F0 – 1F7h 170 – 177h 3F6h and 376h This pin is in TRI-STATE during read or write

accesses to 3F7h and 377h

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