PC87332 datasheet(32/98 Pages) NSC

32 / 98 page

30 FDC Register Description (Continued)

The Mode command can also disable the FIFO for either

reads or writes separately The FIFO allows the system a

larger latency without causing a disk overrununderrun er-

ror The FIFO is typically utilized with multitasking operating

systems andor when running systems at or above a

1 Mbps data rate In its default state the FIFO is disabled

and contains a zero threshold The default state is entered

after a hardware reset

Data Register (FIFO)

DESC

Data 70

RESET

Byte Mode

COND

During the Execution Phase of a command involving a data

transfer tofrom the FIFO

the system must respond

to a data transfer service request based on the following

formula

Maximum Allowable Data Transfer Service Time

(THRESH a 1) c 8 c tDRP b (16 c tICP)

This formula is good for all data rates with the FIFO enabled

or disabled THRESH is a four bit value programmed in the

Configure command which sets the FIFO threshold If the

FIFO is disabled THRESH is zero in the above formula The

last term of the formula (16 c tICP) is an inherent delay due

to the microcode overhead required by the FDC This delay

is also data rate dependent See Table 9-1 for the tDRP and

tICP times See Section 932 for a description of tDRP and

tICP

The programmable FIFO threshold (THRESH) is useful in

adjusting the floppy controller to the speed of the system In

other words a slow system with a sluggish DMA transfer

capability uses a high value of THRESH giving the system

more time to respond to a data transfer service request

(DRQ for DMA mode or IRQ6 for Interrupt mode) Converse-

ly a fast system with quick response to a data transfer serv-

ice request uses a low value of THRESH

318 Digital Input Register (DIR)

Read Only

This diagnostic register is used to detect the state of the

DSKCHG disk interface input and some diagnostic signals

The function of this register depends on its mode of opera-

tion When in the PC-AT mode the D6 – 0 are TRI-STATE to

avoid conflict with the fixed disk status register at the same

address DIR is unaffected by a software reset

DIRPC-AT Mode

DESC

DSKCHG

XXXXXXX

RESET

COND

Disk Changed

Active high status of DSKCHG disk

interface input During power-down this bit is invalid

if it is read by the software

D6 – 0

Unused

by the FDC (at TRI-STATE) The bits are

used by the Hard Disk Controller Status Register

DIRPS2 Mode

DESC

DSKCHG

DRATE1

DRATE0

HIGH

DEN

RESET

COND

Disk Changed

Active high status of DSKCHG disk

interface input During power-down this bit is invalid

if it is read by the software

D6 – 3

Reserved

Always 1

D2 – 1

Data Rate Select 10

These bits indicate the

status of the DRATE1 – 0 bits programmed through

the DSR or CCR

High Density

This bit is low when the 1 Mbps

2 Mbps or 500 kbps data rate is chosen and high

when the 300 kbps or 250 kbps data rate is chosen

This bit is independent of the IDENT value

DIRModel 30 Mode

D6 D5 D4

DESC

DSKCHG

DMAEN NOPRE DRATE1 DRATE0

RESET

COND

Disk Changed

Active low status of DSKCHG disk

interface input During power-down this bit is invalid

if it is read by the software

D6 – 4

Reserved

Always 0

DMA Enable

Active high status of the DMAEN bit

in the DOR

No Precompensation

Active high status of the

NOPRE bit in the CCR

D1 – 0

Data Rate Select 10

These bits indicate the

status of the DRATE 1 – 0 bits programmed through

the DSR or CCR

319 Configuration Control Register (CCR)

Write Only

This is the write-only data rate register commonly used in

PC-AT applications This register is not affected by a soft-

ware reset and is set to 250 kbps after a hardware reset

The data rate of the floppy controller is determined by the

last write to either the CCR or DSR

CCRPC-AT and PS2 Modes

DESC

000000

DRATE1

DRATE0

RESET

COND

D7–2

Reserved

Should be set to 0

D1 – 0

Data Rate Select 10

These bits determine the

data rate of the floppy controller See Table 3-7 for

the appropriate values

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