PC87332 datasheet(78/98 Pages) NSC

78 / 98 page

70 Parallel Port (Continued)

The FIFO does not stall when overwritten or underrun (ac-

cess is ignored) Bytes are always read from the top of the

FIFO regardless of the direction bit (bit 5 of DCR) For ex-

ample if 44h 33h 22h 11h are written into the FIFO read-

ing the FIFO returns 44h 33h 22h 11h (in the same order it

was written)

CNFGA

Configuration Register A Read only Reading this

no effect and the data is ignored

CNFGB

Configuration Register B Read only Reading this

and its state as follows

Bit 7

This bit is always 0

Bit 6

Holds the (non-inverted) value on the configured

IRQ pin

Bits 5 4

These bits are 1 when IRQ5 is configured and 0

when IRQ7 is configured

Bit 3

This bit is always 1

Bits 2

These bits are always 0 Writing to this register

1 0

has no effect and the data is ignored

ECR

Extended Control Register This register controls

the ECP and parallel port functions On reset this

driven low on an ECR read when the ECR status

bits do not hold updated data

Bit 7

These three bits determine the mode of operation

6 5

(Mode) Bit 7 is the MSB

000 Standard mode Write cycles are performed

under software control

Bit 5 of DCR is forced to 0 (forward direction)

and PD0 – 7 is driven The FIFO is reset (emp-

ty)

001 PS2 mode Read and write cycles are per-

formed under software control The FIFO is

reset (empty)

010 Parallel Port FIFO mode Write cycles are

performed under hardware control (STB is

controlled by hardware) Bit 5 of DCR is

forced to 0 (forward direction) and PD0 – 7

are driven

011 ECP FIFO mode The FIFO direction is con-

trolled by bit 5 of DCR

Read and write cycles to the device are per-

formed under hardware control (STB and

AFD are controlled by hardware)

100 Reserved

101 Reserved

110 FIFO test mode The FIFO is accessible via

the TFIFO register

The ECP does not issue ECP cycles to fill

empty the FIFO

111 Configuration

mode

The

CNFGA

and

CNFGB registers are accessible in this

mode

Bit 4

ECP Interrupt Mask bit When this bit is 0 an inter-

rupt is generated on ERR assertion (the high-to-

low edge of ERR) An interrupt is also generated

when ERR is asserted while this bit is changed

from 1 to 0 this prevents the loss of an interrupt

between an ECR read and ECR write When this

bit is 1 no interrupt is generated

Bit 3

ECP DMA Enable bit When this bit is 0 DMA is

disabled and the PDRQ pin is in TRI-STATE

When this bit is 1 DMA is enabled and DMA starts

when bit 2 of ECR is 0

Note

PDACK is assumed inactive when this bit is 0

Bit 2

ECP Service bit When this bit is 0 and one of the

following three interrupt events occur an interrupt

is generated and this bit is set to 1 by hardware

1 Bit 3 of ECR is 1 and terminal count is reached

during DMA

2 Bit 3 of ECR is 0 and bit 5 of DCR is 0 and

there are eight or more bytes free in the FIFO

3 Bit 3 of ECR is 0 and bit 5 of DCR is 1 and

there are eight or more bytes to be read from the

FIFO

When this bit is 1 DMA and the above three inter-

rupts are disabled

Writing 1 to this bit does not cause an interrupt

When the ECP clock is frozen this bit is read as 0

regardless of its actual value (even though the bit

may be modified by software when the ECP clock

is frozen)

Bit 1

FIFO Full bit Read only

This bit is 0 when the FIFO has at least one free

byte

This bit is 1 when the FIFO is full

This bit continuously reflects the FIFO state and

therefore can only be read Data written to this bit

is ignored

When the ECP clock is frozen this bit is read as 1

regardless of the actual FIFO state

Bit 0

FIFO Empty bit Read only

This bit is 0 when the FIFO has at least one byte

of data

This bit is 1 when the FIFO is empty

This bit continuously reflects the FIFO state and

therefore can only be read Data written to this bit

is ignored

When the ECP clock is frozen this bit is read as 1

regardless of the actual FIFO state

78 SOFTWARE CONTROLLED DATA TRANSFER

(Modes 000 and 001)

Software controlled data transfer is supported in modes 000

and 001 The software generates peripheral-device cycles

by modifying the DATAR and DCR registers and reading the

DSR DCR and DATAR registers The negotiation phase

and nibble mode transfer as defined in the IEEE 1284 stan-

dard are performed in these modes

In these modes the FIFO is reset (empty) and is not func-

tional The DMA and RLE are idle

Mode 000 is for the forward direction only the direction bit

is forced to 0 and PD0 – 7 is driven Mode 001 is for both the

forward and backward directions The direction bit controls

whether PD0 – 7 are driven

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