PC87311 datasheet(18/78 Pages) NSC

18 / 78 page

30 FDC Register Description (Continued)

TLF11362 – 4

FIGURE 3-1 FDC Functional Block Diagram

The FDC contains write precompensation circuitry that will

default to 125 ns for 250 300 and 500 kbs (4167 ns at

1 Mbs) These values can be overridden in software to

disable write precompensation or to provide levels of pre-

compensation up to 250 ns The FDC has internal 24 mA

data bus buffers which allow direct connection to the sys-

tem bus The internal 40 mA totem-pole disk interface buff-

ers are compatible with both CMOS drive inputs and 150X

resistor terminated disk drive inputs

The following FDC registers are mapped into the addresses

shown below with the base address range being provided

by the on-chip address decoder pin For PC-AT or PS2

applications the diskette controller primary address range is

3F0 to 3F7 (hex) and the secondary address range is 370

to 377 (hex) The FDC supports three different register

modes the PC-AT mode PS2 mode (Micro Channel sys-

tems) and the Model 30 mode (Model 30) See Section 51

for more details on how each register mode is enabled

When applicable the register definition for each mode of

operation will be given If no special notes are made then

the register is valid for all three register modes

TABLE 3-1 Register Description and Addresses

A1 A0

IDENT

Status Register A

SRA

Status Register B

SRB

RW Digital Output Register

DOR

RW Tape Drive Register

TDR

Main Status Register

MSR

Data Rate Select Register

DSR

RW Data Register (FIFO)

FIFO

None (Bus TRI-STATE)

Digital Input Register

DIR

Configuration Control Register

CCR

Note

SRA and SRB are enabled by IDENT e 0 during a chip reset only

31 STATUS REGISTER A (SRA)

Read Only

This is a read-only diagnostic register that is part of the

PS2 floppy controller register set and is enabled when in

the PS2 or Model 30 mode This register monitors the state

of the IRQ6 pin and some of the disk interface signals The

SRA can be read at any time when in PS2 mode In the

PC-AT mode D7 – D0 are TRI-STATE during a mP read

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