PC87311 datasheet(24/78 Pages) NSC

24 / 78 page

30 FDC Register Description

(Continued)

Missing Address Mark

If bit 0 of ST2 is clear then

the controller cannot detect any Address Field Ad-

dress Mark after two disk revolutions If bit 0 of ST2

is set then the controller cannot detect the Data

Field Address Mark after finding the correct Ad-

dress Field

3103 Status Register 2 (ST2)

DESC

SEH

SNS

RESET

000

COND

Not Used Always 0

Control Mark

Controller tried to read a sector

which contained a deleted data address mark dur-

ing execution of Read Data or Scan commands Or

if a Read Deleted Data command was executed a

regular address mark was detected

CRC Error in Data Field

Controller detected a

CRC error in the Data Field Bit 5 of ST1 is also set

Wrong Track

Only set if desired sector is not

found and the track number recorded on any sector

of the current track is different from the track ad-

dress specified in the Command Phase

Scan Equal Hit

‘‘Equal’’ condition satisfied during

any Scan command

Scan Not Satisfied

Controller cannot find a sector

on the track which meets the desired condition dur-

ing any Scan command

Bad Track

Only set if the desired sector is not

found the track number recorded on any sector on

the track is FF (hex) indicating a hard error in IBM

format and is different from the track address spec-

ified in the Command Phase

Missing Address Mark in Data Field

Controller

cannot find the Data Field AM during a Read Scan

or Verify command Bit 0 of ST1 is also set

3104 Status Register 3 (ST3)

DESC

TK0

HDS

DS1

DS0

RESET

101

COND

Not Used Always 0

Write Protect

Indicates active high status of the

WP pin

Not Used Always 1

Track 0

Indicates active high status of the TRK0

Not Used Always 1

Head Select

Indicates the active high status of the

HD bit in the Command Phase

D1D0 Drive Select 10

These two binary encoded bits

indicate the DS1DS0 bits in the Command Phase

40 FDC Command Set Description

The following is a table of the FDC command set Each

command contains a unique first command byte called the

opcode byte which will identify to the controller how many

command bytes to expect If an invalid command byte is

issued to the controller it will immediately go into the Result

Phase and the status will be 80 (hex) which signifies Invalid

Command

41 COMMAND SET SUMMARY

CONFIGURE

Command Phase

0011

0000

EIS

FIFO

POLL

THRESH

PRETRK

Execution Phase

Internal registers written

No Result Phase

DUMPREG

Command Phase

00001110

Execution Phase

Internal registers read

Result Phase

PTR Drive 0

PTR Drive 1

PTR Drive 2

PTR Drive 3

Step Rate Time

Motor Off Time

Motor On Time

DMA

Sector per TrackEnd of Track

LOCK

DC3

DC2

DC1

DC0

GAP

EIS

FIFO

POLL

THRESH

PRETRK

Note

Sectors per Track parameter returned if last command issued was

Format End of Track parameter returned if last command issued was Read

or Write

FORMAT TRACK

Command Phase

MFM

XXXHDDR1

DR0

Bytes per Sector

Sectors per Track

Format Gap

Data Pattern

Execution Phase

System transfers four ID bytes (track

head sector bytessector) per sector to the floppy control-

ler via DMA or Non-DMA modes The entire track is format-

ted The data block in the Data Field of each sector is filled

with the data pattern byte

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