PC87311 datasheet(53/78 Pages) NSC

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60 Serial Ports (Continued)

Bit 3

This bit enables the interrupt when set No exter-

nal pin is associated with this bit In Local Loop-

back Mode this bit controls bit 7 of the MODEM

Status Register

Bit 4

This bit provides a Local loopback feature for diag-

nostic testing of the UART When bit 4 is set to

logic 1 the following occur the transmitter Serial

Output (SOUT) is set to the Marking (logic 1) state

the receiver Serial Input (SIN) is disconnected the

output of the Transmitter Shift Register is ‘‘looped

back’’ (connected) to the Receiver Shift Register

the four MODEM Control inputs (DSR CTS RI

and DCD) are disconnected and the DTR RTS

OUT1 IRQ ENABLE bits in MCR are internally

connected to DSR CTS RI and DCD in MSR re-

spectively When operating in the AT mode the

MODEM Control output pins are forced to their

high (inactive) states When operating in the XT

mode the Modem Control output pins remain con-

nected to their corresponding bits in the MCR In

the Loopback Mode data that is transmitted is im-

mediately received This feature allows the proc-

essor to verify the transmit-and-received-data

paths of the serial port

In the Loopback Mode the receiver and transmit-

ter interrupts are fully operational The MODEM

Status Interrupts are also operational but the in-

terrupts’ sources are the lower four bits of MCR

instead of the four MODEM control inputs Writing

a 1 to any of these 4 MCR bits will cause an inter-

rupt In Loopback Mode the interrupts are still con-

trolled by the Interrupt Enable Register The IRQ3

and 4 pins respond as follows in Loopback mode

(1) If AT mode is set (see XTSEL pin) then the

IRQ3 and 4 pins are TRI-STATE If XT mode is set

then the IRQ3 and 4 pins will be TRI-STATE only if

the MCR3 bit is low

Bits 5 – 7

These bits are permanently set to logic 0

628 Modem Status Register (MSR)

This register provides the current state of the control lines

from the MODEM (or peripheral device) to the CPU In addi-

tion to this current-state information four bits of the MO-

DEM Status Register provide change information These

bits are set to a logic 1 whenever a control input from the

MODEM changes state They are reset to logic 0 whenever

the CPU reads the MODEM Status Register Table 6-2

shows the contents of the MSR Details on each bit follow

Bit 0

This bit is the Delta Clear to Send (DCTS) indicator

Bit 0 indicates that the CTS input to the chip has

changed state since the last time it was read by the

CPU

Bit 1

This bit is the Delta Data Set Ready (DDSR) indica-

tor Bit 1 indicates that the DSR input to the chip has

changed state since the last time it was read by the

CPU

Bit 2

This bit is the Trailing Edge of Ring Indicator (TERI)

detector Bit 2 indicates that the RI input to the chip

has changed from a low to a high state

Bit 3

This bit is the Delta Data Carrier Detect (DDCD) in-

dicator Bit 3 indicates that the DCD input to the

chip has changed state

Note

Whenever bit 0 1 2 or 3 is set to logic 1 a MODEM Status

Interrupt is generated

Bit 4

This bit is the complement of the Clear to Send

(CTS) input If bit 4 (loopback) of the MCR is set to a

1 this bit is equivalent to RTS in the MCR

Bit 5

This bit is the complement of the Data Set Ready

(DSR) input If bit 4 of the MCR is set to a 1 this bit

is equivalent to DTR in the MCR

Bit 6

This bit is the complement of the Ring Indicator (RI)

input If bit 4 of the MCR is set to a 1 this bit is

equivalent to OUT1 in the MCR

Bit 7

This bit is the complement of the Data Carrier De-

tect (DCD) input If bit 4 of the MCR is set to a 1 this

bit is equivalent to IRQ ENABLE in the MCR

629 Scratchpad Register (SCR)

This 8-bit ReadWrite Register does not control the UART

in any way It is intended as a scratchpad register to be used

by the programmer to hold data temporarily When operat-

ing in the XT mode this register is unavailable

63 PC87312 SERIAL PORTS

631 Serial Port Registers

Two identical register sets one for each channel are in the

PC87312 All register descriptions in this section apply to

the register sets in both channels

TABLE 6-6 PC87312 UART Register Addresses

(AEN e 0)

DLAB

Selected Register

Receiver Buffer (Read)

Transmitter Holding (Write)

Interrupt Enable

Interrupt Identification (Read)

FIFO Control (Write)

Line Control

MODEM Control

Line Status

MODEM Status

Scratch

Divisor Latch

(Least Significant Byte)

Divisor Latch

(Most Significant Byte)

632 Line Control Register (LCR)

The system programmer uses the Line Control Register

(LCR) to specify the format of the asynchronous data com-

munications exchange and set the Divisor Latch Access bit

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