PC87309VLJ datasheet(163/192 Pages) NSC

163 / 192 page

Mouse and Keyboard Controller (KBC) (Logical Devices 5 and 6)

163

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8.5

INTERNAL KBC - PC87309 INTERFACE

The KBC interfaces internally with the PC87309 via three

registers: an input (DBBIN), output (DBBOUT) and status

(STATUS) register. See FIGURE 8-1 "KBC System Func-

tional Block Diagram" on page 158 and TABLE 8-1 "Sys-

tem Interface Operations".

TABLE 8-1. System Interface Operations

TABLE 8-1 "System Interface Operations" illustrates the

use of address line A2 to differentiate between data and

commands. The device is selected by chip identification of

default address 60h (when A2 is 0) or 64h (when A2 is 1).

After reset, these addresses can be changed by software.

8.5.1

The KBC DBBOUT Register, Offset 60h,

Read Only

The DBBOUT register transfers data from the keyboard

controller to the PC87309. It is written to by the keyboard

controller and read by the PC87309 for transfer to the PC.

The PC may be notified of the need to read data from the

KBC by an interrupt request or by polling the Output Buffer

Full (OBF) bit (bit 0 of the KBC STATUS register described

in Section 8.5.3 "The KBC STATUS Register").

8.5.2

The KBC DBBIN Register, Offset 60h (F1 Clear)

or 64h (F1 Set), Write Only

The DBBIN register transfers data from the PC87309 sys-

tem to the keyboard controller. (This transaction is transpar-

ent to the user, who should program the device as if direct

access to the registers were in effect.)

When data is received in this manner, an Input Buffer Full

(IBF) internal interrupt may be generated in the KBC, to deal

with this data. Alternatively, reception of data in this manner

can be detected by the KBC polling the Input Buffer Full bit

(IBF, bit 1 of the KBC STATUS register).

8.5.3

The KBC STATUS Register

The STATUS register holds information regarding the sys-

tem interface status.The bitmap below shows the bit defini-

tion of this register. This register is controlled by the KBC

firmware and hardware, and is read-only for the system.

Bit 0 - OBF, Output Buffer Full

A 1 indicates that data has been written into the DB-

BOUT register by the KBC. It is cleared by a system

read operation from DBBOUT.

Bit 1 - IBF, Input Buffer Full

When a write operation is performed by the host system,

this bit is set to 1, which may be set up to trigger the IBF

interrupt. Upon executing an IN A, DBB instruction, it is

cleared.

Bit 2 - F0, General Purpose Flag

A general purpose flag that can be cleared or toggled by

the keyboard controller firmware.

Bit 3 - F1, Command/Data Flag

This flag holds the state of address line A2 while a write

operation is performed by the host system. It distin-

guishes between commands and data from the host

system. In this device, a write with A2 = 1 (hence F1 =

1) is defined as a command, and A2 = 0 (hence F1 = 0)

is data.

Bits 7-4, General Purpose Flags

These flags may be modified by KBC firmware.

8.6

INSTRUCTION TIMING

The KBC clock is first divided by 3 to generate the state tim-

ing, then by 5 to generate the instruction timing. Thus each

instruction cycle consists of five states and 15 clock cycles.

Most keyboard controller instructions require only one in-

struction cycle, while some require two cycles. Refer to the

8042 or PC87323VUL instruction set for details.

RD WR

Default

Addresses

Operation

60h

Read DBBOUT

60h

Write DBBIN, F1 Clear (Data)

64h

Read STATUS

64h

Write DBBIN, F1 Set (Command)

76543210

Reset

OBF Output Buffer Full

IBF Input Buffer Full

F0 General Purpose Flag

F1 Command or Data Flag

General Purpose

Flags

KBC Status Register

Offset 64h

Read Only

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