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PC87309VLJ датащи(PDF) 166 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали PC87309VLJ
подробное описание детали  PC87309 SuperI/O Plug and Play Compatible Chip in Compact 100-Pin VLJ Packaging
PDF  192 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87309VLJ датащи(HTML) 166 Page - National Semiconductor (TI)

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Device Specifications
166
www.national.com
10.2 DC CHARACTERISTICS OF PINS, BY GROUP
The following tables list the DC characteristics of all device pins described in Section 1.2. The pin list preceeding each table
lists the device pins to which the table applies.
10.2.1
Group 1
Pin List:
A11-0, AEN, CLKIN, CTS2,1, DACK3-1, DCD2,1, DSKCHG, DSR2,1, ID3-0, INDEX, IORD, IOWR, MR, RDATA, RI2,1,
SIN2,1, TC, TRK0, WP
All Group 1 pins are back-drive protected.
1. Not tested. Guaranteed by design.
10.2.2
Group 2
Pin List:
BUSY, PE, SLCT, WAIT
Output from SLCT, PE and BUSY is open-drain in all SPP modes, except in SPP Compatible mode when the setup mode
is ECP-based FIFO and bit 4 of the Control2 parallel port register is 1. (See TABLE 4-1 "Parallel Port Mode Selection" on
page 80.) Otherwise, output from these signals is level 2. External 4.7 K
Ω pull-up resistors should be used.
PE is in Group 2 only if bit 2 of PP Confg0 Register is “0” (see Section 4.5.19 "PP Confg0 Register" on page 94).
All group 2 pins are back-drive protected.
1. Not tested. Guaranteed by design.
10.2.3
Group 3
Pin List:
ACK, ERR, PE
Output from ACK and ERR is open-drain in all SPP modes, except in SPP Compatible mode when the setup mode is ECP-
based FIFO and bit 4 of the Control2 parallel port register is 1. (See TABLE 4-1 "Parallel Port Mode Selection" on page 80.)
Otherwise, output from these signals is level 2.
External 4.7 K
Ω pull-up resistors should be used.
PE is in Group 3 only if bit 2 of PP Confg0 Register is “1” (see Section 4.5.19 "PP Confg0 Register" on page 94).
All group 3 pins are back-drive protected.
1. Not tested. Guaranteed by design.
Symbol Parameter
Conditions
Min
Max
Unit
VIH
Input High Voltage
2.0
VDD
1
V
VIL
Input Low Voltage
−0.51
0.8
V
IIL
Input Leakage Current
VIN = VDD
10
µA
VIN = VSS
−10
µA
VH
Input Hysteresis
250
mV
Symbol Parameter
Conditions
Min
Max
Unit
VIH
Input High Voltage
2.0
VDD
1
V
VIL
Input Low Voltage
−0.51
0.8
V
IIL
Input Leakage Current
VIN = VDD
120
µA
VIN = VSS
−10
µA
Symbol Parameter
Conditions
Min
Max
Unit
VIH
Input High Voltage
2.0
VDD
1
V
VIL
Input Low Voltage
−0.51
0.8
V
IIL
Input Leakage Current
VIN = VDD
10
µA
VIN = VSS
−120
µA



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