PC87309VLJ datasheet(161/192 Pages) NSC

161 / 192 page

Mouse and Keyboard Controller (KBC) (Logical Devices 5 and 6)

161

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FIGURE 8-5. Timing Generation and Timer Circuit

8.3.3

KBC Clock

The KBC clock frequency is selected by the SuperI/O KBC

Configuration Register at index F0h of Logical Device 6 to

be either 8, 12 or 16 MHz.

For details regarding the configuration of each device, refer

to TABLES 2-17 "KBC Configuration Registers for Key-

board - Logical Device 6" and 2-16 "KBC Configuration

Registers for Mouse - Logical Device 5" on page 27.

8.3.4

Timer or Event Counter

The keyboard controller includes an 8-bit counter, which

can be used as a timer or an event counter, as selected by

the firmware.

Timer Operation

When the internal clock is chosen as the counter input, the

counter functions as a timer. The clock fed to the timer con-

sists of the KBC instruction cycle clock, divided by 32. (See

FIGURES 8-4 "Instruction Timing" on page 160 and FIG-

URE 8-5 "Timing Generation and Timer Circuit".) The divi-

sor is reset only by a hardware reset or when the timer is

started by an STRT T instruction.

Event Counter Operation

When the clock input of the counter is switched to the exter-

nal input (MCLK), it becomes an event counter. The falling

edge of the signal on the MCLK pin causes the counter to

increment. Timer Overflow Flag and Timer interrupt operate

as in the timer mode.

8.4

EXTERNAL I/O INTERFACES

The PC chip set interfaces with the PC87309 as illustrated

in FIGURE 8-2 "System Interfaces" on page 159.

All data transactions between the KBC and the PC chip set

are handled by the PC87309.

The PC87309 decodes all I/O device chip-select functions

from the address bus. The KBC chip-select codes are, tra-

ditionally, 60h or 64h, as described in TABLE 8-1 "System

Interface Operations" on page 163. (These addresses are

user-programmable.)

The external interface includes two sets of signals: the key-

board and mouse interface signals, and the general-pur-

pose I/O signals.

8.4.1

Keyboard and Mouse Interface

Four serial I/O signals interface with the external keyboard

and mouse. These signals are driven by open-collector driv-

ers with signals derived from two I/O ports residing on the

internal bus. Each output can drive 16 mA, making them

suitable for driving the keyboard and mouse cables. The

signals are named KBCLK, KBDAT, MCLK and MDAT, and

they are the logical complements of P26, P27, P23 and

P22, respectively.

TEST0 and TEST1 are dedicated test pins, internally con-

nected to KBCLK and MCLK, respectively, as shown in FIG-

URES 8-1

"KBC System Functional Block Diagram" on

page 158 and 8-2 "System Interfaces" on page 159. These

pins may be used as logical conditions for conditional jump

instructions, which directly check the logical levels at the

pins.

KBDAT and MDAT are connected to pins P10 and P11, re-

spectively.

MCLK also provides input to the event counter.

External

TEST1

3-State

5-Cycle

32-Bit

Timer

Prescaler

8-Bit Timer

or Counter

Overflow

Flag

Stop

Counter

Timer

Counter

Interrupt

(MCLK)

CLKIN

External Event Input

48 MHz

Clock

KBC Clock

2 or 3

÷ 2

Select

Frequency

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