December 2000

9

MICRF007

MICRF007

Micrel

I/O Pin Interface Circuitry

Interface circuitry for the various I/O pins of the MICRF007

are diagrammed in Figures 1 through 6. The ESD protection

diodes at all input and output pins are not shown.

ANT Pin

50

3pF

6k

Active

Load

Active

Bias

ANT

Figure 1a. ANT Pin

The ANT pin is internally AC-coupled via a 3pF capacitor, to

an RF N-channel MOSFET, as shown in Figure 1. Impedance

on this pin to VSS is quite high at low frequencies, and

decreases as frequency increases. In the UHF frequency

range, the device input can be modeled as 6.3k

Ω in parallel

with 2pF (pin capacitance) shunt to VSS0RF.

CTH Pin

6.9pF

PHI2B

PHI1B

PHI1

PHI2

CTH

Demodulator

Signal

2.85Vdc

VDDBB

VSSBB

VSSBB

Figure 2. CTH Pin

Figure 2 illustrates the CTH-pin interface circuit. The CTH pin

is driven from a P-channel MOSFET source-follower with

approximately 10

µA of bias. Transmission gates TG1 and

TG2 isolate the 6.9pF capacitor. Internal control signals

PHI1/PHI2 are related in a manner such that the impedance

across the transmission gates looks like a “resistance” of

approximately 100k

Ω. The dc potential at the CTH pin is

approximately 1.6V

CAGC Pin

VDDBB

VSSBB

675µA

67.5µA

Compa-

rator

1.5µA

15µA

Timout

CAGC

Figure 3. CAGC Pin

Figure 3 illustrates the CAGC pin interface circuit. The AGC

control voltage is developed as an integrated current into a

capacitor C

the decay current is a 1/10th scaling of this, nominally 1.5

µA,

making the attack/decay timeconstant ratio a fixed 10:1.

Signal gain of the RF/IF strip inside the IC diminishes as the

voltage at CAGC decreases. Modification of the attack/decay

ratio is possible by adding resistance from the CAGC pin to

V

Both the push and pull current sources are disabled during

shutdown, which maintains the voltage across C

improves recovery time in duty-cycled applications. To fur-

ther improve duty-cycle recovery, both push and pull currents

are increased by 45 times for approximately 10ms after

release of the SHUT pin. This allows rapid recovery of any

voltage droop on C

DO Pin

VDDBB

VSSBB

Compa-

rator

10µA

10µA

DO

Figure 4. DO Pin

The output stage for DO (digital output) is shown in Figure 4.

The output is a 10

µA push and 10µA pull switched-current

stage. This output stage is capable of driving CMOS loads.

An external buffer-driver is recommended for driving high-

capacitance loads.

REFOSC Pin

250

Ω

200k

Active

Bias

REFOSC

30pF

30pF

30µA

VDDBB

VSSBB

VSSBB

Figure 5. REFOSC Pin

The REFOSC input circuit is shown in Figure 5. Input imped-

ance is high (200k

Ω). This is a Colpitts oscillator with internal

30pF capacitors. This input is intended to work with standard

ceramic resonators connected from this pin to the VSS pin,

although a crystal may be used when greater frequency

accuracy is required. The nominal dc bias voltage on this pin

is 1.4V.