December 2000

7

MICRF007

MICRF007

Micrel

Functional Description

Refer to “MICRF007 Block Diagram”. Identified in the block

diagram are the three sections of the IC: UHF Downconverter,

OOK Demodulator and Reference and Control, and Wakeup.

Also shown in the figure are two capacitors (C

one timing component (Y1), usually a crystal. With the

exception of a supply decoupling capacitor, these are the only

external components needed by the MICRF007 to assemble

a complete UHF receiver. There is one control input, the

SHUT pin. The SHUT function is used to enable the reciever.

These inputs are CMOS compatible, and are pulled-up on the

IC.

Receiver Operation

The MICRF007 is a standard superheterodyne receiver with

a narrow RF bandwidth IF. The narrow bandwidth receiver is

less susceptible to interfering RF signals. The MICRF007 is

capable of data rates up to 2.1kbps. Typically a crystal is

used for the reference oscillator frequency. The MICRF007

RF center frequency is controlled by a completely integrated

PLL / VCO frequency synthesizer which is referenced to the

crystal frequency.

Since the MICRF007 bandwidth is 430kHz, a tight tolerance

transmitter must be used for the system. Typically SAW or

crystal based transmitters are used in application designs.

IF Bandpass Filter

Rolloff response of the IF Filter is 5th order, while the

demodulator data filter exhibits a 2nd order response.

Baseband Demodulator Filter Bandwidth

The MICRF007 has a fully intergrated baseband demodula-

tor filter. The filter has a fixed 2.1kHz bandwidth. This filter

limits the reciever raw data rate to 2kbps.

Functional Diagram

Peak

Detector

AGC

Control

2nd Order

Programmable

Low-Pass Filter

5th Order

Band-Pass Filter

Programmable

Synthesizer

Control

Logic

Reference

Oscillator

Cystal

or

Ceramic

Resonator

CAGC

ANT

VDD

VSS

REFOSC

430kHz

Switched-

Capacitor

Resistor

CTH

DO

MICRF002

RF

Amp

IF

Amp

IF

Amp

Compa-

rator

Reference and Control

UHF Downconverter

OOK Demodulator

SHUT

MICRF007 Block Diagram

Data Slicing Level

Extraction of the dc value of the demodulated signal for

purposes of logic-level data slicing is accomplished using the

external threshold capacitor C

capacitor “resistor” R

effective resistance of R

Slicing level time constant values vary somewhat with de-

coder type, data pattern, and data rate, but typically values

range from 5ms to 50ms. Optimization of the value of C

required to maximize range.

Automatic Gain Control

The signal path has AGC (automatic gain control) to increase

input dynamic range. An external capacitor, C

connected to the CAGC pin of the device. The ratio of decay-

to-attack time-constant is fixed at 10:1 (that is, the attack time

constant is 1/10th of the decay time constant), and this ratio

cannot be changed by the user. However, the attack time

constant is set externally by choosing a value for C

The AGC control voltage is carefully managed on-chip to

allow duty-cycle operation of the MICRF007 in excess of

100:1. When the device is placed into shutdown mode (SHUT

pin pulled high), the AGC capacitor floats, to retain the

voltage. When operation is resumed, only the voltage droop

on the capacitor due to leakage must be replenished, there-

fore a relatively low-leakage capacitor is recommended for

duty-cycled operation. The actual tolerable leakage will be

application dependent. Clearly, leakage performance is less

critical when the device off-time is low (milliseconds) and

more critical when the off-time is high (seconds).

To further enhance duty-cycled operation of the IC, the AGC

push and pull currents are increased for a fixed time immedi-

ately after the device is taken out of shutdown mode (turned-

on). This compensates for AGC capacitor voltage droop

while the IC is in shutdown mode, reduces the time to restore

the correct AGC voltage, and therefore extends maximum