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LM9830 датащи(PDF) 19 Page - National Semiconductor (TI) |
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LM9830 датащи(HTML) 19 Page - National Semiconductor (TI) |
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19 / 45 page ![]() 19 http://www.national.com DIGITAL PIXEL RATE OFFSET AND GAIN SETTINGS 3E Multiplier Gain Range Smaller gain ranges provide finer control. Larger gain ranges correct for larger shading errors. 0 0 1.5:1 (33%) 0 1 2.0:1 (50%) 1 0 3.0:1 (66%) 1 1 Bypass Multiplier Offset/Gain data format 0 6 bits offset/10 bits gain 1 8 bits offset/8 bits gain Multiplier Coefficient Source 0 Configuration Register 3F (Fixed) 1 External SRAM Offset Coefficient Source 0 Configuration Register 40 and 41 (Fixed) 1 External SRAM 3F Fixed Offset Coefficient n nnnnnnn Fixed Offset to use for calibration - 2MSBs are assumed to be 0 if using 6 bit offset format 40 Fixed Multiplier Coefficient - MSB n n Fixed Gain to use for calibration - 2LSBs are assumed to be 0 if using 8 bit gain format 41 Fixed Multiplier Coefficient - LSB n nnnnnnn PARALLEL PORT SETTINGS 42 Communication Mode (for reading data from any of the LM9830’s registers) Note: This register must be set appropriately before data can be read from the LM9830! 0 8 bit Bidirectional/EPP 1 4 bit Nibble Parallel Port Output Driver Current (IOL and IOH can be used to calculate rise and fall times into the load capacitance: rise/fall time approximately equals 5V*C/i) 00 IOL = 5mA, IOH = -6mA 01 IOL = 7mA, IOH = -9mA 10 IOL = 9mA, IOH = -12mA 11 IOL = 15mA, IOH = -21mA EXTERNAL SRAM SETTINGS 43 External SRAM Size 0 0 64 kbytes (not recommended for 600dpi scanners) 0 1 128 kbytes 1 0 256 kbytes 11 N/A SRAM Interface Output Driver Current (IOL and IOH can be used to calculate rise and fall times into the load capacitance: rise/fall time approximately equals 5V*C/i) 00 IOL = 3.5mA, IOH = -4mA 01 IOL = 6mA, IOH = -7.5mA 10 IOL = 12mA, IOH = -17mA 11 IOL = 21mA, IOH = -32mA SRAM Bandwidth (8 Bit Data Mode) 8 slot mode should always be used to maximize performance. If the external SRAM is to slow to meet the tRD SETUP requirement, the slower 4 SRAM accesses/ADC clock mode may be used. 0 4 SRAM accesses/ADC clock 1 8 SRAM accesses/ADC clock (fMCLK must be 25MHz or lower) Scanning Duplex (10/12 bit Data Mode) Full Duplex mode should always be used to maximize scan speed. If the external SRAM is to slow to meet the tRD SETUP requirement, the slower Half Duplex mode may be used. 0 Full Duplex- Can transmit data while scanning (fMCLK must be 25MHz or lower) 1 Half Duplex - Can only transmit data when buffer is full or scan has been stopped Address Function D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Value |
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