WM9713 datasheet(20/111 Pages) WOLFSON

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WM9713L

Preliminary Technical Data

PTD, March 2004, Rev 2.2

PEN ADC

The clock for the PENADC nominally runs at 768kHz and is derived from BITCLK. The divisor for the

clock generator is set by PENDIV. This enables the PENADC clock frequency to be set according to

power consumption and conversion rate considerations.

PLL MODE

The PLL operation is controlled by register 46h (see Table 3) and has two modes of operation:

•

Integer N

•

Fractional N

The PLL has been optimized for nominal input clock (PLL_IN) frequencies in the range 8.192MHz –

19.661MHz (LF=0) and 2.048MHz – 4.9152MHz (LF=1).

Through use of a clock divider (div by 2 / 4) on the input to the PLL frequencies up to 78.6MHz can

be accommodated. The input clock divider is enabled by DIVSEL (0=Off) and the division ratio is set

by DIVCTL (0=div2, 1=div4).

Figure 3 PLL Architecture

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

15:12

N[3:0]

0000

PLL integer division control (must be set

between 5-12 for integer N mode)

0 = off

Allows PLL operation with low frequency

input clocks (< 8.192MHz)

SDM

0 = off

Sigma Delta Modulator enable. Allows

fractional N division

DIVSEL

0 = off

Enables input clock to PLL to be divided by

2 or 4. Use if input clock is above 14.4MHz

DIVCTL

Controls division mode when DIVSEL is

high. 0 = div by 2, 1= div by 4.

6:4

PGADDR

000

Pager address bits to access programming

of K[21:0] and SPLL[7:0]

46h

3:0

PGDATA

0000

Pager data bits

Table 3 PLL Clock Control

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