WM9713 datasheet(50/111 Pages) WOLFSON

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WM9713L

Preliminary Technical Data

PTD, March 2004, Rev 2.2

ANALOGUE AUDIO OUTPUTS

The following sections give an overview of the analogue audio output pins. The WM9713L has three

outputs capable of driving loads down to 16

Ω (headphone / line drivers) – HPL, HPR and MONO -

and four output capable of driving loads down to 8

Ω (loudspeaker / line drivers) – SPKL, SPKR,

OUT3 and OUT4. The combination of output drivers, mixers and mixer inverters means that many

output configurations can be supported.

For examples of typical output and mixer configurations please refer to the “Typical Output

Configurations” section. For more information on recommended external components, please refer to

the “Applications Information” section.

Each output is driven by a PGA with a gain range of 0dB to -46.5dB in -1.5dB steps. Each PGA has

an input source mux, mute and zero-cross detect circuit (delaying gain changes until a zero-cross is

detected, or after time-out).

HEADPHONE OUTPUTS – HPL AND HPR

The HPL and HPR outputs (pins 39 and 41) are designed to drive a 16

Ω or 32Ω headphone load.

They can also be used as line outputs. They can be used in and AC coupled or DC coupled (capless)

configuration. The available input sources are HPMIXL/R and Vmid (see Table 31).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

7:6

HPL

00 (Vmid)

HPL input source select

00: Vmid

01: no i/p (ZH if buffer disabled)

10: HPMIXL

11: unused

1Ch

Output PGA

Mux Select

5:4

HPR

00 (Vmid)

HPR input source select

00: Vmid

01: no i/p (ZH if buffer disabled)

10: HPMIXR

11: unused

Table 31 HPL / HPR PGA Input Source

The signal volume on HPL and HPR can be independently adjusted under software control by writing

to register 04h.

When not in use HPL and HPR can be powered down using the Powerdown register bits HPL and

HPR (register 3Eh, bits [10:9]). To minimise pops and clicks when the PGA is powered down / up it is

recommended that the Vmid input is selected during the power down / up cycle. This ensures the

same DC level is maintained on the output pin throughout.

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