ADUCM350BBCZ datasheet(31/41 Pages) AD

31 / 41 page

ADuCM350

Data Sheet

Rev. A | Page 30 of 40

ANALOG FRONT END

Figure 37. AFE System Block Diagram

For full details on the ADuCM350, refer to the UG-587

hardware reference manual.

The ADuCM350 is a high accuracy, configurable, AFE with a

low power, peripheral rich, microcontroller subsystem.

EXCITATION STAGE

The excitation/transmit stage consists of a 12-bit DAC with an

excitation buffer and an instrumentation amplifier in a feedback

path to the DAC, which forces an accurate voltage across the

impedance to be measured, thereby removing parasitics from

the measurement system.

All measurements are referenced to a precision external resistor,

which is used in the internal calibration loop to ensure no dc

bias across an unknown impedance.

A large range of impedances can be measured, depending on

the application. Users can optimize the calibration resistor

(RCAL), ac amplitude of the excitation waveform, and the

current-to-voltage (IV) resistor to tailor fit the system to the

application demands. Impedances can be measured from 80 Hz

to ~75 kHz.

The switch matrix offers the user full configurability with 34

user selectable switches. The current carrying switches on both

excitation buffer output and the transimpedance input are opti-

mally sized for current loads. The switch matrix allows the device

to measure and store offset and gain results. The ADuCM350

can self calibrate Rx offset and gain, Tx offset and gain, and

switch leakage. This off loads the requirement for an extensive

factory calibration routine and removes temperature and aging

induced errors from measurements.

RCAL 1

AFE 1

AFE 2

AFE 3

AFE 4

AFE 5

AFE 6

AFE 7

AFE 8

SWITCH

MATRIX

EXCITATION

AMPLIFIER

RCAL

RCAL 2

ATTEN

1 OR 40

TEMP

SENS

VBIAS

TIA_I

RTIA

TIA_O

AN_A

AN_B

AN_C

AN_D

VCCM

DVDD

AVDD

LP RCF

50kHz

AAF

55kHz

GAIN

1 OR 1.5

ADC

MUX

12-BIT

DAC

GAIN AND

OFFSET

CAL

VREFDAC

326.53kSPS

160kSPS

16-BIT

ADC

GAIN AND

OFFSET

CAL

DFT

N = 2048

(12.8ms)

HANN

WINDOW

VREFADC

DAC CODE

(ARBITRARY)

178

SINC2HF

SINC2LF

50Hz/60Hz

REJECTION

SINE

GENERATION

TRAPEZOID

GENERATION

900SPS

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