ADUCM350 datasheet(18/41 Pages) AD

номер детали	ADUCM350

подробное описание детали	16-Bit Precision, Low Power Meter On A

PDF	41 Pages

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производитель	AD [Analog Devices]

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18 / 41 page

Data Sheet

ADuCM350

Rev. A | Page 17 of 40

Figure 6. SPI Master Mode Timing (Phase Mode = 0)

Table 32. SPI Slave Mode Timing

Parameter

Description

Min

Typ

Max

Unit

CS to SCLK edge

tSL

SCLK low pulse width1

(SPIXDIV[5:0] + 1) × tUCLK

tSH

SCLK high pulse width1

62.5

(SPIDIV[5:0] + 1) × tUCLK

tDAV

Data output valid after SCLK edge

49.1

tDSU

Data input setup time before SCLK edge

20.2

tDHD

Data input hold time after SCLK edge

10.1

tDF

Data output fall time

35.5

tDR

Data output rise time

35.5

tSR

SCLK rise time

35.5

tSF

SCLK fall time

35.5

tDOCS

Data output valid after CS edge

tSFS

CS high after SCLK edge

1 tUCLK = 62.5 ns. It corresponds to the maximum internal clock frequency before clock dividers.

Figure 7. SPI Slave Mode Timing (Phase Mode = 1)

SCLK

(POLARITY = 0)

SCLK

(POLARITY = 1)

MOSI

MSB

BIT 6 TO BIT 1

LSB

MISO

MSB IN

BIT 6 TO BIT 1

LSB IN

tSH

tSR

tSF

tDR

tDF

tDAV

tDOSU

tDSU

tDHD

1 SCLK CYCLE

tCS

tSL

1 SCLK CYCLE

tSFS

SCLK

(POLARITY = 0)

SCLK

(POLARITY = 1)

tSH

tSL

tSR

tSF

tSFS

MISO

MSB

BIT 6 TO BIT 1

LSB

MOSI

MSB IN

BIT 6 TO BIT 1

LSB IN

tDHD

tDSU

tDAV

tDR

tDF

tCS

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