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ADUCM350 датащи(PDF) 14 Page - Analog Devices

номер детали ADUCM350
подробное описание детали  16-Bit Precision, Low Power Meter On A
PDF  41 Pages
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производитель  AD [Analog Devices]
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ADUCM350 датащи(HTML) 14 Page - Analog Devices

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Data Sheet
ADuCM350
Rev. A | Page 13 of 40
TIMING CHARACTERISTICS
LCD Segment/Common Timing Specifications
Table 26. LCD Segment/Common Timing Specifications1,2
FRAMESEL[3]
FRAMESEL[2]
FRAMESEL[1]
FRAMESEL[0]
Static Mux
4× Mux
fLCD (Hz)
Frame Rate (Hz)
fLCD (Hz)
Frame Rate (Hz)
0
0
0
0
256
128
1024
128
0
0
0
1
204.8
102.4
819.2
102.4
0
0
1
0
170.7
85.3
682.7
85.3
0
0
1
1
146.3
73.1
585.1
73.1
0
1
0
0
128
64
512
64
0
1
0
1
113.8
56.9
455.1
56.9
0
1
1
0
102.4
51.2
409.6
51.2
0
1
1
1
93.1
46.5
372.4
46.5
1
0
0
0
85.3
42.7
341.3
42.7
1
0
0
1
78.8
39.4
315.1
39.4
1
0
1
0
73.1
36.6
292.6
36.6
1
0
1
1
68.3
34.1
273.1
34.1
1
1
0
0
64
32
256
32
1
1
0
1
60.2
30.1
240.9
30.1
1
1
1
0
56.9
28.4
227.6
28.4
1
1
1
1
53.9
26.9
215.6
26.9
1
fLCD = fBCLK/(FRAMESEL + 4). See the UG-587 hardware reference manual for details
2
FRAMESEL[3], FRAMESEL[2], FRAMESEL[1], and FRAMESEL[0] indicate the bit numbers in the LCD_COM register.
I2C Timing
Capacitive load for each of the I2C bus lines (CB) = 400 pF maximum as per I2C bus specifications; I2C timing is guaranteed by design and
not production tested.
Table 27. I2C Timing in Fast Mode (400 kHz)
Parameter
Description
Min
Max
Unit
tL
Clock low pulse width
1300
ns
tH
Clock high pulse width
600
ns
tSHD
Start condition hold time
600
ns
tDSU
Data setup time
100
ns
tDHD1
Data hold time
0
ns
tRSU
Setup time for repeated start
600
ns
tPSU
Stop condition setup time
600
ns
tBUF
Bus-free time between a stop condition and a start condition
1.3
μs
tR
Rise time for both clock and data
20 + 0.1 Cb
300
ns
tF
Fall time for both clock and data
20 + 0.1 Cb
300
ns
tSUP
Pulse width of spike suppressed
0
50
ns
1
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VINH (minimum) of the SCL signal) to bridge the undefined region
of the falling edge of SCL.
Table 28. I2C Timing in Standard Mode (100 kHz)
Parameter
Description
Min
Max
Unit
tL
Clock low pulse width
4.7
μs
tH
Clock high pulse width
4.0
ns
tSHD
Start condition hold time
4.7
μs
tDSU
Data setup time
250
ns
tDHD1
Data hold time
0
μs
tRSU
Setup time for repeated start
4.0
μs



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