ADUCM350 datasheet(16/41 Pages) AD

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Data Sheet

ADuCM350

Rev. A | Page 15 of 40

I2S Timing Specifications

I2S timing is guaranteed by design and not production tested; timing specifications are given for a standard I2S data rate of 2.5 MHz; the

I2S bus is designed to operate up to 25 MHz.

Table 29. I2S Timing: Master Transmitter

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments1

I2S MASTER TRANSMITTER TIMING

SCLK Period

360

400

440

Minimum Clock Period

TTR

360

TTR is the minimum allowed clock

period for the transmitter, T > TTR

Clock High Period

tHC

160

Minimum > 0.35 × T = 140 ns

Clock Low Period

tLC

160

Minimum > 0.35 × T = 140 ns

Delay

tDTR

300

Minimum < 0.80 × T = 320 ns

Data Hold Time

tHTR

100

Minimum > 0 ns

Clock Rise Time

tRC

Minimum > 0.15 × TTR = 54 ns (slave

mode only)

1 T refers to the typical value listed for the SCLK period; therefore, T = 400 ns in this case.

Table 30. I2S Timing: Slave Receiver

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments1

I2S SLAVE RECEIVER TIMING

SCLK Period

360

400

440

TTR = 360 ns

Clock High Period

tHC

110

Minimum < 0.35 × T = 126 ns

Clock Low Period

tLC

160

Minimum < 0.35 × T = 126 ns

Data Setup Time

tSR

300

Minimum < 0.20 × T = 72 ns

Data Hold Time

tHTR

100

Minimum < 0 ns

1 T refers to the typical value listed for the SCLK period; therefore, T = 400 ns in this case.

Figure 3. I2S-Compatible Interface Transmitter Timing

SCLK

SD/WS

NOTES

1. SD = SERIAL DATA, WS = WORD SELECT, WS = 0: CHANNEL 1 (LEFT), WS = 1: CHANNEL 2 (RIGHT).

tRC IS ONLY RELEVANT FOR TRANSMITTERS IN SLAVE MODE.

tRC*

tHTR ≥ 0

tLC ≥ 0.35T

tHC ≥ 0.35T

VH = 2.0V

VL = 0.8V

tDTR ≤ 0.8T

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