AD9163BBCZ datasheet(65/124 Pages) AD

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AD9163

Data Sheet

Rev. 0 | Page 64 of 123

For example, a sine wave with no digital backoff ideally measures

6 dBm. If a typical balun loss of 1.2 dB is included, expect to

measure 4.8 dBm of actual power in the region where the sinc

response of the DAC has negligible influence and analog roll-off

has not begun. Increasing the output power is best accomplished

by increasing IOUTFS. An example of DAC output characteristics

for several balun and board types is shown in Figure 138.

Output Stage Configuration

The AD9163 is intended to serve high dynamic range applications

that require wide signal reconstruction bandwidth (such as a

DOCSIS cable modem termination system (CMTS)) and/or

high IF/RF signal generation. Optimum ac performance can be

realized only when the DAC output is configured for differential

(that is, balanced) operation with its output common-mode

voltage biased to a stable, low noise 2.5 V nominal analog

supply (VDD25_DAC).

The output network used to interface to the DAC provides a near

0 Ω dc bias path to VDD25_DAC. Any imbalance in the output

impedance over frequency between the OUTPUT+ and

OUTPUT− pins degrades the distortion performance (mostly

even order) and noise performance. Component selection and

layout are critical in realizing the performance potential of the

AD9163.

Most applications that require balanced to unbalanced conversion

from 10 MHz to 3 GHz can take advantage of several available

transformers that offer impedance ratios of both 2:1 and 1:1.

Figure 137 shows the AD9163 interfacing to the Mini-Circuits

TCM1-63AX+ and the TC1-1-43X+ transformers.

50Ω

MINI-CIRCUITS

TCM1-63AX+

TC1-1-43X+

OUTPUT+

OUTPUT–

VDD25_DAC

Figure 137. Recommended Transformer for Wideband Applications with

Upper Bandwidths of up to 5 GHz

–5

–10

–15

–20

fOUT (GHz)

BAL-0006

TC1-1-43X+

TCM1-63AX+

Figure 138. Measured DAC Output Response; fDAC = 6 GSPS

To assist in matching the AD9163 output, an equivalent model

of the output was developed, and is shown in Figure 139. This

equivalent model includes all effects from the ideal 40 mA

current source in the die to the ball of the CSP_ BGA package,

including parasitic capacitance, trace inductance and resistance,

contact resistance of solder bumps, via inductance, and other

effects.

3.59Ω

470pH

40mA

179Ω

1.14pF

248fF

OUTPUT–

OUTPUT+

Figure 139. Equivalent Circuit Model of the DAC Output

A Smith chart is provided in Figure 140 showing the simulated

S11 of the DAC output, using the model in Figure 139. The plot

was taken using the circuit in Figure 139, with an ideal balun.

For the measured response of the DAC output, see Figure 138.

5.0

–5.0

2.0

1.0

–1.0

FREQUENCY (10MHz TO 6GHz)

–2.0

0.5

–0.5

0.2

–0.2

FREQUENCY = 10MHz

S (1, 1) = 0.770/149.556

IMPEDANCE = Z0 × (0.140 + j0.267)

FREQUENCY = 100MHz

S (1, 1) = 0.227/163.083

IMPEDANCE = Z0 × (0.638 + j0.089)

FREQUENCY = 1GHz

S (1, 1) = 0.367/–144.722

IMPEDANCE = Z0 × (0.499 – j0.245)

FREQUENCY = 2GHz

S (1, 1) = 0.583/–148.777

IMPEDANCE = Z0 × (0.282 – j0.259)

FREQUENCY = 4GHz

S (1, 1) = 0.794/–170.517

IMPEDANCE = Z0 × (0.116 – j0.082)

FREQUENCY = 6GHz

S (1, 1) = 0.779/168.448

IMPEDANCE = Z0 × (0.125 + j0.100)

Figure 140. Simulated Smith Chart Showing the DAC Output Impedance

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