AD9163BBCZ datasheet(58/124 Pages) AD

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Data Sheet

AD9163

Rev. 0 | Page 57 of 123

APPLICATIONS INFORMATION

HARDWARE CONSIDERATIONS

Power Supply Recommendations

All the AD9163 supply domains must remain as noise free as

possible for the best operation. Power supply noise has a

frequency component that affects performance, and is specified in

volts rms terms.

An LC filter on the output of the power supply is recommended

to attenuate the noise, and must be placed as close to the AD9163

as possible. The VDD12_CLK supply is the most noise sensitive

supply on the device, followed by the VDD25_DAC and

VNEG_N1P2 supplies, which are the DAC output rails. It is

highly recommended that the VDD12_CLK be supplied by

itself with an ultralow noise regulator such as the ADM7154 or

ADP1761 to achieve the best phase noise performance possible.

Noisier regulators impose phase noise onto the DAC output.

The VDD12A supply can be connected to the digital DVDD

supply with a separate filter network. All of the SERDES 1.2 V

supplies can be connected to one regulator with separate filter

networks. The IOVDD supply can be connected to the VDD25_

DAC supply with a separate filter network, or can be powered

from a system controller (for example, a microcontroller), 1.8 V

to 3.3 V supply. The power supply sequencing requirement

must be met; therefore, a switch or other solution must be used

when connected to the IOVDD supply with VDD25_DAC.

Take note of the maximum power consumption numbers given

in Table 3 to ensure the power supply design can tolerate tempera-

ture and IC process variation extremes. The amount of current

drawn is dependent on the chosen use cases, and specifications

are provided for several use cases to illustrate examples and

contributions from individual blocks, and to assist in calculating

the maximum required current per supply.

Another consideration for the power supply design is peak

current handling capability. The AD9163 draws more current in

the main digital supply when synthesizing a signal with

significant amplitude variations, such as a modulated signal, as

compared to when in idle mode or synthesizing a dc signal.

Therefore, the power supply must be able to supply current

quickly to accommodate burst signals such as GSM, TDMA, or

other signals that have an on/off time domain response. Because

the amount of current variation depends on the signals used, it

is best to perform lab testing first to establish ranges. A typical

difference can be several hundred milliamperes.

Power Sequencing

The AD9163 requires power sequencing to avoid damage to the

DAC. A board design with the AD9163 must include a power

sequencer chip, such as the ADM1184, to ensure that the

domains power up in the correct order. The ADM1184 monitors

the level of power domains upon power-up. It sends an enable

signal to the next grouping of power domains. When all power

domains are powered up, a power-good signal is sent to the

system controller to indicate all power supplies are powered up.

The IOVDD, VDD12A, VDD12_CLK, and DVDD domains

must be powered up first. Then, the VNEG_N1P2, VDD_1P2,

PLL_CLK_VDD12, DVDD_1P2, and SYNC_VDD_3P3 can be

powered up. The VDD25_DAC domain must be powered up

last. There is no requirement for a power-down sequence.

Power and Ground Planes

Solid ground planes are recommended to avoid ground loops

and to provide a solid, uninterrupted ground reference for the

high speed transmission lines that require controlled impedances.

It is recommended that power planes be stacked between

ground layers for high frequency filtering. Doing so adds extra

filtering and isolation between power supply domains in

addition to the decoupling capacitors.

Do not use segmented power planes as a reference for controlled

impedances unless the entire length of the controlled impedance

trace traverses across only a single segmented plane. These and

additional guidelines for the topology of high speed transmission

lines are described in the JESD204B Serial Interface Inputs

(SERDIN0± to SERDIN7±) section.

For some applications, where highest performance and higher

output frequencies are required, the choice of PCB materials

significantly impacts results. For example, materials such as

polyimide or materials from the Rogers Corporation can be

used, for example, to improve tolerance to high temperatures

and improve performance. Rogers 4350 material is used for the

top three layers in some of the evaluation board designs:

between the top signal layer and the ground layer below it,

between the ground layer and an internal signal layer, and

between that signal layer and another ground layer.

JESD204B Serial Interface Inputs (SERDIN0± to

SERDIN7±)

When considering the layout of the JESD204B serial interface

transmission lines, there are many factors to consider to

maintain optimal link performance. Among these factors are

insertion loss, return loss, signal skew, and the topology of the

differential traces.

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