ICS952607 datasheet(10/21 Pages) ICST

10 / 21 page

Integrated

Circuit

Systems, Inc.

ICS952607

Advance Information

0734—07/16/04

Table 4: Mode Selection Table

Mode

Standard Overclock Mode

CPU Overclock Mode

Graphic Overclock Mode

IIC Control

Byte 5 bit(6:5) = 00

Byte 5 bit(6:5) = 01

Byte 5 bit(6:5) = 10

CPU M/N Overclocking

Byte 11 & 12

SRC M/N Overclocking

Byte 11 & 12

Byte 5 & 6 (asynchronous)

Byte 11 & 12

AGP/PCI M/N Overclocking

Byte 11 & 12

Byte 5 & 6 (asynchronous)

Spreading

All clocks have spread.

Only CPU clocks have spread.

Latch input shoud be set as

FS(4:0) = 10xxx. CPU & SRC

have spread.

Remark

All clocks oveclock together by

Byte 11&12 M/N programming.

CPU overclock by Byte 11&12

SRC/AGP/PCI overclock by Byte

5&6 asynchronously.

CPU/SRC overclock by Byte

11&12 AGP/PCI overclock by

Byte 5&6 asynchronously.

Mode B (B6&B3 bit 7) AGP/PCI

can be selected to be overclock

from 66/33, 72/36 or 80/40.

Simple async AGP/PCI

overclocking w/o using M/N

programming.

SRC can be kept at 100 w/o

spread yet AGP/PCI can be

overclocked.

Simple async AGP/PCI

overclocking w/o using M/N

programming.

Table 5: Asynchronous 3V66/PCI Frequency Table

Byte6 Bit7

Byte3 Bit7

3V66/PCI Frequency

66.66/33.33

80.00/40.00

72.73/36.36

2C Table: Vendor & Revision ID Register

Control

Function

Bit 7

ASEL0

3V66/PCI Freq Select

Bit 6

N PLL2 Div6

Bit 5

N PLL2 Div5

Bit 4

N PLL2 Div4

Bit 3

N PLL2 Div3

Bit 2

N PLL2 Div2

Bit 1

N PLL2 Div1

Bit 0

N PLL2 Div0

2C Table: Vendor & Revision ID Register

Control

Function

Bit 7

RID3

Bit 6

RID2

Bit 5

RID1

Bit 4

RID0

Bit 3

VID3

Bit 2

VID2

Bit 1

VID1

Bit 0

VID0

The decimal representation of N PLL2 Div

(6:0) + 8 is equal to VCO divider value for

PLL2.

Byte 6

Pin #

Name

PWD

N Divider

Programming bits for

Async mode 2&3

See Table 4: Async AGP/PCI Freq Table

Type

VENDOR ID

PWD

REVISION ID

Byte 7

Pin #

Name

Type

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