2

Integrated

Circuit

Systems, Inc.

ICS952607

Advance Information

0734—07/16/04

Pin Description

PIN

#

PIN NAME

PIN TYPE

DESCRIPTION

1

*FS1/REF0

I/O

Frequency select latch input pin / 14.318 MHz reference clock.

2

*FS0/REF1

I/O

Frequency select latch input pin / 14.318 MHz reference clock.

3

REF2

OUT

14.318 MHz reference clock.

4

VDDREF

PWR

Ref, XTAL power supply, nominal 3.3V

5

X1

IN

Crystal input,nominally 14.318MHz.

6

X2

OUT

Crystal output, Nominally 14.318MHz

7

GND

PWR

Ground pin.

8

**FS2/PCICLK_F0

I/O

Frequency select latch input pin / 3.3V PCI free running clock output.

9

**FS4/PCICLK_F1

I/O

Frequency select latch input pin / 3.3V PCI free running clock output.

10

PCICLK_F2

OUT

Free running PCI clock not affected by PCI_STOP# .

11

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

12

GND

PWR

Ground pin.

13

^^PCICLK0

OUT

PCI clock output.

14

PCICLK1

OUT

PCI clock output.

15

PCICLK2

OUT

PCI clock output.

16

PCICLK3

OUT

PCI clock output.

17

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

18

GND

PWR

Ground pin.

19

PCICLK4

OUT

PCI clock output.

20

PCICLK5

OUT

PCI clock output.

21

**Sel24_48#/24_48MHz

I/O

Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24mHz, 0 =

48MHz.

22

**FS3/48MHz_0

I/O

Frequency select latch input pin / Fixed 48MHz clock output. 3.3V

23

48MHz_1

OUT

48MHz clock output.

24

GND

PWR

Ground pin.

25

VDD48

PWR

Power for 24 & 48MHz output buffers and fixed PLL core.

26

3V66_3/VCH

OUT

3.3V 66.66MHz clock output / 48MHz VCH clock output.

27

3V66_2

OUT

3.3V 66.66MHz clock output

28

VDD3V66

PWR

Power pin for the 3V66 clocks.

29

GND

PWR

Ground pin.

30

3V66_1

OUT

3.3V 66.66MHz clock output

31

3V66_0

OUT

3.3V 66.66MHz clock output

32

SCLK

IN

Clock pin of I2C circuitry 5V tolerant

33

SDATA

I/O

Data pin for I2C circuitry 5V tolerant

34

VttPWR_GD/PD#

IN

This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs

are valid and are ready to be sampled. This is an active high input. / Asynchronous

active low input pin used to power down the device into a low power state.

35

VDD

PWR

Power supply, nominal 3.3V

36

SRCCLKC

OUT

Complement clock of differential pair for S-ATA support.

+/- 300ppm accuracy required.

37

SRCCLKT

OUT

True clock of differential pair for S-ATA support.

+/- 300ppm accuracy required.

38

GND

PWR

Ground pin.

39

CPUCLKC0

OUT

"Complementary" clocks of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

40

CPUCLKT0

OUT

"True" clocks of differential pair CPU outputs. These are current mode outputs.

External resistors are required for voltage bias.

41

VDDCPU

PWR

Supply for CPU clocks, 3.3V nominal

42

CPUCLKC1

OUT

"Complementary" clocks of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias.

43

CPUCLKT1

OUT

"True" clocks of differential pair CPU outputs. These are current mode outputs.

External resistors are required for voltage bias.

44

GND

PWR

Ground pin.

45

Reset#

OUT

Real time system reset signal for frequency gear ratio change or watchdog timer

timeout. This signal is active low.

46

IREF

OUT

This pin establishes the reference current for the CPUCLK pairs. This pin requires a

fixed precision resistor tied to ground in order to establish the appropriate current.

47

GND

PWR

Ground pin.

48

VDDA

PWR

3.3V power for the PLL core.