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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ICS952607 датащи(PDF) 9 Page - Integrated Circuit Systems |
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ICS952607 датащи(HTML) 9 Page - Integrated Circuit Systems |
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9 / 21 page  9 Integrated Circuit Systems, Inc. ICS952607 Advance Information 0734—07/16/04 I 2C Table: Output Control Register Control Function Bit 7 ASEL1 3V66/PCI Freq Select RW 0 Bit 6 Reserved Reserved RW 0 Bit 5 PCICLK5 Output Control RW 1 Bit 4 PCICLK4 Output Control RW 1 Bit 3 PCICLK3 Output Control RW 1 Bit 2 PCICLK2 Output Control RW 1 Bit 1 PCICLK1 Output Control RW 1 Bit 0 PCICLK0 Output Control RW 1 Disable Enable See Table 5: Async AGP/PCI Freq Table -- Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable PWD - Byte 3 Pin # Name Type 0 1 - 20 19 16 15 14 13 Table 3: Linear M/N AGP/PCI Programmable Frequency Example C 31 65.15 32.58 C 33 67.44 33.72 B 2D 65.24 32.62 7 1E 67.57 33.78 A 29 65.34 32.67 B 2F 67.70 33.85 7 1D 65.79 32.89 A 2B 68.01 34.01 6 19 66.01 33.01 C 34 68.58 34.29 D 36 66.14 33.07 B 30 68.93 34.47 C 32 66.30 33.15 A 2C 69.34 34.67 B 2E 66.47 33.24 C 35 69.73 34.86 A 2A 66.68 33.34 9 28 69.83 34.91 D 37 67.21 33.61 6 1B 70.01 35.01 Hex B5b3:0 Hex B6b6:0 AGP Freq PCI Freq Hex B5b3:0 Hex B6b6:0 AGP Freq PCI Freq I 2C Table: Output Control Register Control Function Bit 7 48MHz_0 2x output drive 0=2x drive RW 0 Bit 6 SRCFS SRC Frequency Select -0 Bit 5 Reserved Reserved RW 0 Bit 4 3V66_1 Output Control RW 1 Bit 3 3V66_0 Output Control RW 1 Bit 2 PCICLK_F2 Output Control RW 1 Bit 1 PCICLK_F1 Output Control RW 1 Bit 0 PCICLK_F0 Output Control RW 1 I 2C Table: Reserved Register Control Function Bit 7 3V66_3/VCH Select Output Select RW 0 Bit 6 Mode Sel1 RW 0 Bit 5 Mode Sel0 RW 0 Bit 4 3V66_3/VCH Output Control RW 1 Bit 3 M PLL2 Div3 RW X Bit 2 M PLL2 Div2 RW X Bit 1 M PLL2 Div1 RW X Bit 0 M PLL2 Div0 RW X 3V66 VCH See Table 4: Mode Selection Table Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable 100MHz 200MHz Disable Enable -- The decimal representation of M PLL2 Div (3:0) + 2 is equal to REF divider value for PLL2 01 01 - - - - PWD 8 Byte 5 Pin # Name Type PWD 2x drive normal Name Type Byte 4 Pin # PLL Mode Selection Bits M Divider Programming bits for Async mode 2&3 26 - - 30 31 10 9 - |
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