3

Integrated

Circuit

Systems, Inc.

ICS9FG108

Advance Information

0823—04/02/04

Pin Description (Continued)

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

25

DIF_STOP#

IN

Active low input to stop differential output clocks.

26

SPREAD

IN

Asynchronous, active high input to enable spread spectrum

functionality.

27

SEL14M_25M#

IN

Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818

MHz, 0 = 25 MHz

28

OE_3**

IN

Active high input for enabling outputs.

0 = tri-state outputs, 1= enable outputs

29

DIF_3#

OUT

0.7V differential complement clock outputs

30

DIF_3

OUT

0.7V differential true clock outputs

31

VDD

PWR

Power supply, nominal 3.3V

32

DIF_2#

OUT

0.7V differential complement clock outputs

33

DIF_2

OUT

0.7V differential true clock outputs

34

OE_2*

IN

Active high input for enabling outputs.

0 = tri-state outputs, 1= enable outputs

35

GND

PWR

Ground pin.

36

VDD

PWR

Power supply, nominal 3.3V

37

OE_1*

IN

Active high input for enabling outputs.

0 = tri-state outputs, 1= enable outputs

38

DIF_1#

OUT

0.7V differential complement clock outputs

39

DIF_1

OUT

0.7V differential true clock outputs

40

VDD

PWR

Power supply, nominal 3.3V

41

DIF_0#

OUT

0.7V differential complement clock outputs

42

DIF_0

OUT

0.7V differential true clock outputs

43

OE_0**

IN

Active high input for enabling outputs.

0 = tri-state outputs, 1= enable outputs

44

FS1

IN

Frequency select pin.

45

FS0

IN

Frequency select pin.

46

IREF

OUT

This pin establishes the reference current for the differential current-

mode output pairs. This pin requires a fixed precision resistor tied

to ground in order to establish the appropriate current. 475 ohms is

the standard value.

47

GNDA

PWR

Ground pin for the PLL core.

48

VDDA

PWR

3.3V power for the PLL core.

Note:

Pin names followed by '**' have 120 Kohm pull DOWN resistors

Pin names followed by '*' have 120 Kohm pull UP resistors