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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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UPSD323X датащи(PDF) 44 Page - STMicroelectronics |
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UPSD323X датащи(HTML) 44 Page - STMicroelectronics |
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44 / 176 page  µPSD323X 44/176 POWER-SAVING MODE Two software selectable modes of reduced power consumption are implemented. Idle Mode The following Functions are Switched Off. – CPU (Halted) The following Function Remain Active During Idle Mode. – External Interrupts – Timer0, Timer1, Timer2 – DDC Interface – PWM Units – USB Interface – USART – 8-bit ADC –I2C Interface Note: Interrupt or RESET terminates the Idle Mode. Power-Down Mode – System Clock Halted – LVD Logic Remains Active – SRAM contents remains unchanged – The SFRs retain their value until a RESET is as- serted Note: The only way to exit Power-down Mode is a RESET. Table 25. Power-Saving Mode Power Consumption Power Control Register The Idle and Power-down Modes are activated by software via the PCON register. Table 26. Pin Status During Idle and Power-down Mode Table 27. Description of the PCON Bits Note: 1. See the T2CON register for details of the flag description Mode Addr/Data Ports1,3,4 PWM I2C DDC USB Idle Maintain Data Maintain Data Active Active Active Active Power-down Maintain Data Maintain Data Disable Disable Disable Disable SFR Addr Reg Name Bit Register Name Reset Value Comments 7 6 54 321 0 87 PCON SMOD SMOD1 LVREN ADSFINT RCLK1 TCLK1 PD IDLE 00 Power Ctrl Bit Symbol Function 7 SMOD Double baud data rate bit UART 6 SMOD1 Double baud data rate bit 2nd UART 5 LVREN LVR disable bit (active High) 4 ADSFINT Enable ADC interrupt 3 RCLK11 Received clock flag (UART 2) 2 TCLK11 Transmit clock flag (UART 2) 1 PD Activate Power-down Mode (High enable) 0 IDL Activate Idle Mode (High enable) |
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