UPSD323X datasheet(9/176 Pages) STMICROELECTRONICS

9 / 176 page

9/176

µPSD323X

RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . .... . . . .... .... .. . .... .. . .... 140

Warm RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... ... . ... . . .. .. .. .. . . . . . . ... . ...140

I/O Pin, Register and PLD Status at RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Reset of Flash Memory Erase and Program Cycles . . . . . . . . . . . . . . .... ... . . . ... .. .. .. .. 140

Reset (RESET) Timing (Figure 71.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . ... .. . . ... ..140

Status During Power-on RESET, Warm RESET and Power-down Mode (Table 105.). . . . . . . . . 141

PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . ...142

Standard JTAG Signals. .... .. . .... . ... .. . . . . . ... . ... .. . . ... .. . .... . ... .. . . ... ..142

JTAG Port Signals (Table 106.). . .... . ... .. . . . . .... . ... .. . . ... .. . . . . . . ... .. . . ... ..142

JTAG Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...142

Security and Flash memory Protection . . . . . . . . . . .... . ... .. . . ... .. . . . . . . ... .. . . ... ..142

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . ... ..142

AC/DC PARAMETERS . . . . . . .... . ... .. . . ... .. . .... . ... .. .. .. .... . . . ... . . . . . . . . .... 143

PLD ICC /Frequency Consumption (5V range) (Figure 72.) . . . . . .... .. . . . . . . ... .. . .... . . 143

PLD ICC /Frequency Consumption (3V range) (Figure 73.) . . . . . .... .. . . . . . . ... .. . .... . . 143

PSD MODULE Example, Typ. Power Calculation at VCC = 5.0V (Turbo Mode Off) (Table 107.). 144

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . ... . . . . ... .. ... .. .. ... .. . ... .. . . ... . . . . 145

Absolute Maximum Ratings (Table 108.) . . . . . . . . . . . . . . .... . . . .... .... .. . .... .. . .... 145

DC AND AC PARAMETERS. . . . . . . .... . ... .. . . . . .... .... .. . . . . . . . . . . . . . ... .. . .... . . 146

Operating Conditions (5V Devices) (Table 109.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...146

Operating Conditions (3V Devices) (Table 110.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...146

AC Symbols for Timing (Table 111.) . . . . . . . . . . . . . . . . . . . . . . . . . .... .... .. . . . . . . . . .... 147

Switching Waveforms – Key (Figure 74.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

DC Characteristics (5V Devices) (Table 112.). . . . . . . ... . . . . . . . . . .... ... . . . . . . . . . . . . . . 148

DC Characteristics (3V Devices) (Table 113.). . . . . . . ... . . . . . . . . . .... ... . . . . . . . . . . . . . . 150

External Program Memory READ Cycle (Figure 75.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

External Program Memory AC Characteristics (with the 5V MCU Module) (Table 114.) . . . . . . . 152

External Program Memory AC Characteristics (with the 3V MCU Module) (Table 115.) . . . . . . . 153

External Clock Drive (with the 5V MCU Module) (Table 116.) . . . . . . . . . . . . . . . . . . . . . . . . ...153

External Clock Drive (with the 3V MCU Module) (Table 117.) . . . . . . . . . . . . . . . . . . . . . . . . ...153

External Data Memory READ Cycle (Figure 76.) . . . . . . . . .... .... ... . . . . . . . . ... .. . . ... 154

External Data Memory WRITE Cycle (Figure 77.). . . . . . . . . . . . . . . . . . . . . . . . . . . .... . ... ..154

External Data Memory AC Characteristics (with the 5V MCU Module) (Table 118.). .... . ... ..155

External Data Memory AC Characteristics (with the 3V MCU Module) (Table 119.). .... . ... ..156

A/D Analog Specification (Table 120.). . . . . . . . . . . . . . . . . .... . . . .... .... .. . .... .. . .... 156

Input to Output Disable / Enable (Figure 78.) . . . . . .... . . . ... . . . . . . . . . . . . . ... ... . . . ...157

CPLD Combinatorial Timing (5V Devices) (Table 121.) . .... .. . . . . . . . . . . . . . ... .. . .... . . 157

CPLD Combinatorial Timing (3V Devices) (Table 122.) . .... .. . . . . . . . . . . . . . ... .. . .... . . 157

Synchronous Clock Mode Timing – PLD (Figure 79.) . . . . . . . . . . . . .... . . . ... . . . . . . . . . . . . 158

CPLD Macrocell Synchronous Clock Mode Timing (5V Devices) (Table 123.) .... .. .. ... .. .. 158

CPLD Macrocell Synchronous Clock Mode Timing (3V Devices) (Table 124.) .... .. .. ... .. .. 159

Asynchronous RESET / Preset (Figure 80.) . . . . . . .... . . . ... . . . . . . . . . . . . . ... ... . . . ...160

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