UPSD323X datasheet(70/176 Pages) STMICROELECTRONICS

70 / 176 page

µPSD323X

70/176

ANALOG-TO-DIGITAL CONVERTOR (ADC)

The analog to digital (A/D) converter allows con-

version of an analog input to a corresponding 8-bit

digital value. The A/D module has four analog in-

puts, which are multiplexed into one sample and

hold. The output of the sample and hold is the in-

put into the converter, which generates the result

via successive approximation. The analog supply

voltage is connected to AVREF of ladder resis-

tance of A/D module.

The A/D module has two registers which are the

control register ACON and A/D result register

ADAT. The register ACON, shown in Table 47,

page 71, controls the operation of the A/D convert-

er module. To use analog inputs, I/O is selected by

P1SFS register. Also an 8-bit prescaler ASCL di-

vides the main system clock input down to approx-

imately 6MHz clock that is required for the ADC

logic. Appropriate values need to be loaded into

the prescaler based upon the main MCU clock fre-

quency prior to use.

The processing of conversion starts when the

Start Bit ADST is set to ’1.’ After one cycle, it is

cleared by hardware. The register ADAT contains

the results of the A/D conversion. When conver-

sion is completed, the result is loaded into the

ADAT the A/D Conversion Status Bit ADSF is set

to ’1.’

The block diagram of the A/D module is shown in

Figure 35. The A/D Status Bit ADSF is set auto-

matically when A/D conversion is completed,

cleared when A/D conversion is in process.

The ASCL should be loaded with a value that re-

sults in a clock rate of approximately 6MHz for the

ADC using the following formula:

ADC clock input = (Fosc / 2) / (Prescaler register

value +1)

Where Fosc is the MCU clock input frequency

The conversion time for the ADC can be calculat-

ed as follows:

ADC Conversion Time = 8 clock * 8bits * (ADC

Clock) ~= 10.67usec (at 6MHz)

ADC Interrupt

The ADSF Bit in the ACON register is set to ’1’

when the A/D conversion is complete. The status

bit can be driven by the MCU, or it can be config-

ured to generate a falling edge interrupt when the

conversion is complete.

The ADSF interrupt is enabled by setting the ADS-

FINT Bit in the PCON register. Once the bit is set,

the external INT1 interrupt is disabled and the

ADSF interrupt takes over as INT1. INT1 must be

configured as if it is an edge interrupt input. The

INP1 pin (p3.3) is available for general I/O func-

tions, or Timer1 gate control.

Figure 35. A/D Block Diagram

AI06627

Input

MUX

ACH0

ACH1

ACH2

ACH3

ACON

INTERNAL BUS

ADAT

AVREF

Ladder

Resistor

ecode

S/H

Successive

Approximation

Circuit

Conversion

Complete

Interrupt

UPSD323X датащи(PDF) 70 Page - STMicroelectronics

UPSD323X датащи(HTML) 70 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL