12

COMMERCIALTEMPERATURERANGE

BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36

Data is read from the FIFO to the B0-B35 outputs by a LOW-to-HIGH

transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is

LOW, and EF/OR is HIGH (see Table 3). FIFO reads on Port B are

independent of any concurrent writes on Port A.

The setup and hold time constraints to the port clocks for the port Chip

SelectsandWrite/Readselectsareonlyforenablingwriteandreadoperations

andarenotrelatedtohigh-impedancecontrolofthedataoutputs. Ifaportenable

isLOWduringaclockcycle,theport’sChipSelectandWrite/Readselectmay

change states during the setup and hold time window of the cycle.

When operating the FIFO in FWFT mode and the Output Ready flag is

LOW,thenextwordwrittenisautomaticallysenttotheFIFO’soutputregister

bytheLOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflag

HIGH. WhentheOutputReadyflagisHIGH,dataresidingintheFIFO’smemory

array is clocked to the output register only when a read is selected using the

port’sChipSelect,Write/Readselect,Enable,andMailboxselect.

WhenoperatingtheFIFOinIDTStandardmode,regardlessofwhether

theEmptyFlagisLOWorHIGH,dataresidingintheFIFO’smemoryarrayis

clocked to the output register only when a read is selected using the port’s

Chip Select, Write/Read select, Enable, and Mailbox select. Port A Write

timing diagram can be found in Figure 7. Relevant Port B Read timing

diagrams together with Bus-Matching and Endian select can be found in

Figure 8, 9 and 10.

CSB

W/RB

ENB

MBB

CLKB

Data B (B0-B35) I/O

Port Functions

H

X

X

X

X

High-Impedance

None

L

L

L

X

X

Input

None

LL

H

L

↑

Input

None

LL

H

H

↑

Input

Mail2Write

L

H

L

L

X

Output

None

LH

H

L

↑

Output

FIFO read

L

H

L

H

X

Output

None

LH

H

H

↑

Output

Mail1 Read (Set MBF1 HIGH)

TABLE 3 — PORT-B ENABLE FUNCTION TABLE

CSA

W/RA

ENA

MBA

CLKA

Data A (A0-A35) I/O

Port Functions

H

X

X

X

X

High-Impedance

None

L

H

L

X

X

Input

None

LH

H

L

↑

Input

FIFOWrite

LH

H

H

↑

Input

Mail1Write

L

L

L

L

X

Output

None

LL

H

L

↑

Output

None

L

L

L

H

X

Output

None

LL

H

H

↑

Output

Mail2 Read (Set MBF2 HIGH)

TABLE 2 —

—

—

—

— PORT-A ENABLE FUNCTION TABLE

TABLE 4 — FIFO FLAG OPERATION (IDT STANDARD AND FWFT MODES)

Synchronized

Synchronized

to CLKB

to CLKA

EF/OR

AE

AF

FF/IR

000

L

L

H

H

1 to X

1 to X

1 to X

H

L

H

H

(X+1)to[2,048-(Y+1)]

(X+1)to[4,096-(Y+1)]

(X+1)to[8,192-(Y+1)]

H

H

H

H

(2,048-Y)to2,047

(4,096-Y)to4,095

(8,192-Y)to8,191

H

H

L

H

2,048

4,096

8,192

H

H

L

L

NOTES:

1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.

2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no

read operation necessary), it is not included in the memory count.

3. X is the Almost-Empty offset used by AE. Y is the Almost-Full offset used by AF. Both X and Y are selected during a FIFO reset or Port A programming.