10

COMMERCIALTEMPERATURERANGE

BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36

BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)

— ENDIAN SELECTION

Thisisadualpurposepin. AtthetimeofReset,theBEselectfunctionis

active,permittingachoiceofBig-orLittle-Endianbytearrangementfordataread

fromPortB. Thisselectiondeterminestheorderbywhichbytes(orwords)of

dataaretransferredthroughthisport. Forthefollowingillustrations,assume

that a byte (or word) bus size has been selected for Port B. (Note that when

Port B is configured for a long word size, the Big-Endian function has no

A HIGH on the BE/FWFT input when the Reset (RS1) input goes from

LOW to HIGH will select a Big-Endian arrangement. In this case, the most

significantbyte(word)ofthelongwordwrittentoPortAwillbereadfromPort

Bfirst;theleastsignificantbyte(word)ofthelongwordwrittentoPortAwillbe

read from Port B last.

A LOW on the BE/FWFT input when the Reset (RS1) input goes from

LOW to HIGH will select a Little-Endian arrangement. In this case, the least

significantbyte(word)ofthelongwordwrittentoPortAwillbereadfromPort

Bfirst;themostsignificantbyte(word)ofthelongwordwrittentoPortAwillbe

readfromPortBlast. RefertoFigure2foranillustrationoftheBEfunction.See

Figure 3 (Reset) for an Endian select timing diagram.

— TIMING MODE SELECTION

AfterReset,theFWFTselectfunctionisactive,permittingachoicebetween

two possible timing modes: IDT Standard mode or First Word Fall Through

(FWFT)mode. OncetheReset(RS1)inputisHIGH,aHIGHontheBE/FWFT

inputduringthenextLOW-to-HIGHtransitionofCLKA andCLKB willselect

IDTStandardmode. ThismodeusestheEmptyFlagfunction(EF)toindicate

whether or not there are any words present in the FIFO memory. It uses the

Full Flag function (FF) to indicate whether or not the FIFO memory has any

freespaceforwriting. InIDTStandardmode,everywordreadfromtheFIFO,

includingthefirst,mustberequestedusingaformalreadoperation.

Once the Reset (RS1) input is HIGH, a LOW on the BE/FWFT input

duringthenextLOW-to-HIGHtransitionofCLKA andCLKBwillselectFWFT

mode. ThismodeusestheOutputReadyfunction(OR)toindicatewhetheror

notthereisvaliddataatthedataoutputs(B0-B35). ItalsousestheInputReady

function (IR) to indicate whether or not the FIFO memory has any free space

for writing. In the FWFT mode, the first word written to an empty FIFO goes

directlytodataoutputs,noreadrequestnecessary. Subsequentwordsmust

be accessed by performing a formal read operation.

Following Reset, the level applied to the BE/FWFT input to choose the

desiredtimingmodemustremainstaticthroughoutFIFOoperation.Referto

Figure 3 (Reset) for a First Word Fall Through select timing diagram.

PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS

TworegistersintheIDT72V3653/72V3663/72V3673areusedtoholdthe

offsetvaluesfortheAlmost-EmptyandAlmost-Fullflags. TheAlmost-Emptyflag

(AE) Offset register is labeled X and Almost-Full flag (AF) Offset register is

labeledY.Theoffsetregisterscanbeloadedwithpresetvaluesduringthereset

of the FIFO, programmed in parallel using the FIFO’s Port A data inputs, or

programmedinserialusingtheSerialData(SD)input(seeTable1).FS2 FS0/

SD, and FS1/SEN function the same way in both IDT Standard and FWFT

modes.

SIGNAL DESCRIPTION

RESET (RS1, RS2)

Afterpowerup,aResetoperationmustbeperformedbyprovidingaLOW

pulse to RS1 and RS2 simultaneously. Afterwards, the FIFO memory of the

IDT72V3653/72V3663/72V3673 undergoes a complete reset by taking its

Reset(RS1andRS2)inputLOWforatleastfourPortAclock(CLKA)andfour

Port B clock (CLKB) LOW-to-HIGH transitions. The Reset inputs can switch

asynchronously to the clocks. A Reset initializes the internal read and write

pointersandforcestheFull/InputReadyflag(FF/IR)LOW,theEmpty/Output

Readyflag(EF/OR)LOW,theAlmost-Emptyflag(AE)LOW,andtheAlmost-

Full flag (AF) HIGH. A Reset (RS1) also forces the Mailbox flag (MBF1) of

the parallel mailbox register HIGH, and at the same time the RS2 and MBF2

operate likewise. After a Reset, the FIFO’s Full/Input Ready flag is set HIGH

aftertwowriteclockcyclestobeginnormaloperation.

A LOW-to-HIGH transition on the FlFO Reset (RS1) input latches the

valueoftheBig-Endian(BE)inputfordeterminingtheorderbywhichbytesare

transferredthroughPortB.

ALOW-to-HIGHtransitionontheFlFOReset(RS1)inputalsolatchesthe

valuesoftheFlagSelect(FS0,FS1andFS2)inputsforchoosingtheAlmost-

FullandAlmost-Emptyoffsetprogrammingmethod(fordetailsseeTable1,Flag

Programming, and Almost-Empty and Almost-Full flag offset programming

section). The relevant Reset timing diagram can be found in Figure 3.

PARTIAL RESET (PRS)

TheFIFOmemoryoftheIDT72V3653/72V3663/72V3673undergoesa

limited reset by taking its Partial Reset (PRS) input LOW for at least four Port

A clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The

RTMpinmustbeLOWduringthetimeofPartialReset. ThePartialResetinput

canswitchasynchronouslytotheclocks. APartialResetinitializestheinternal

readandwritepointersandforcestheFull/InputReadyflag(FF/IR)LOW,the

Empty/Output Ready flag (EF/OR) LOW, the Almost-Empty flag (AE) LOW,

and the Almost-Full flag (AF) HIGH. A Partial Reset also forces the Mailbox

flag(MBF1,MBF2)oftheparallelmailboxregisterHIGH.AfteraPartialReset,

theFIFO’sFull/InputReadyflagissetHIGHaftertwoWriteClockcyclestobegin

normal operation. See Figure 4, Partial Reset (IDT Standard and FWFT

Modes)fortherelevanttimingdiagram.

Whateverflagoffsets,programmingmethod(parallelorserial),andtiming

mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial

Resetisinitiated,thosesettingswillberemainunchangeduponcompletionof

the reset operation. A Partial Reset may be useful in the case where

reprogramming a FIFO following a Reset would be inconvenient.

RETRANSMIT (RT)

The FIFO memory of these devices undergoes a Retransmit by taking its

associated Retransmit (RT) input LOW for at least four Port A Clock (CLKA)

and four Port B Clock (CLKB) LOW-to-HIGH transitions. The Retransmit

initializesthereadpointerofFIFOtothefirstmemorylocation.

TheRTMpinmustbeHIGHduringthetimeofRetransmit.Notethatthe RT

inputismuxedwiththePRSinput,thestateoftheRTMpindeterminingwhether

thispinperformsaRetransmitoraPartialReset.SeeFigure19forRetransmit

(Standard IDT mode) and figure 20 for Retransmit (FWFT mode) timing

diagrams.

NOTE:

1. Either a HIGH or LOW can be applied to a “don’t care” input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily “don’t care” (along with unused

inputs) must not be left open, rather they must be either HIGH or LOW.