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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STGAP1ASTR датащи(PDF) 63 Page - STMicroelectronics |
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STGAP1ASTR датащи(HTML) 63 Page - STMicroelectronics |
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63 / 70 page  DocID029344 Rev 2 63/70 STGAP1AS Programming manual 70 A description of the STATUS3 register bits is provided in Table 53. 9.2.9 TEST1 register (isolated side) The TEST1 register has the structure of Table 54. Setting an one check bit of the register enables the respective check mode. Table 53. STATUS3 register description Name Bit Fault Latched Force “safe state” Note DT_ERR 4 Deadtime error flag. This bit is forced high when a violation of internal DT is detected. Always No See details in Section 7.2 on page 26 SPI_ERR 3 SPI communication error flag. It is forced high when the SPI communication fails cause: – Wrong CRC check. – Wrong number of CK rising edges. – Attempt to execute a not-allowed command. Attempt to read, write or reset at a not- available address. Always No - REGERRL 2 Register or communication error on low voltage side. It is forced high when: - – Programming procedure is not correctly performed. – Isolated interface communication fails. – An unexpected register value change occurs in one of the remote registers. It is latched at power-up/reset also. Always Yes - OVLOD 1 VDD overvoltage flag. It is forced high when VDD is over OVVDDoff threshold. Always Yes - UVLOD 0 VDD undervoltage flag. It is forced high when VDD is below VDDon threshold. It is latched at power-up/reset also. Always Yes - Table 54. TEST1 register - Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - GOFFCHK GONCHK DESCHK SNSCHK RCHK Default/reset x x x 0 0 0 0 0 |
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