STGAP1ASTR datasheet(62/70 Pages) STMICROELECTRONICS

62 / 70 page

Programming manual

STGAP1AS

62/70

DocID029344 Rev 2

9.2.7

STATUS2 register (low voltage side)

The STATUS2 is a read only register. The STATUS2 register has the structure of Table 50.

A description of the STATUS2 register bits is provided in Table 51.

9.2.8

STATUS3 register (low voltage side)

The STATUS3 is a read only register. The STATUS3 register has the structure of Table 52.

Table 50. STATUS2 register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

REGERRR

ASC

Default(1)

Reset

1. Default value of the local copy of the register. The value will be updated according to the actual information from the

isolated side. The default is forced at the device power-up, when the registers are reset all the flags are forced low (no

failures).

Table 51. STATUS2 register description

Name

Bit

Fault

Latched

Force

“safe state”

Note

REGERRR

It is forced high when:

– Programming procedure is not correctly

performed.

– Isolated interface communication fails.

– An unexpected register value change occurs in

one of the remote registers.

It is also latched at power-up/reset and from Sleep

state.

Always

Yes

ASC

ASC pin status.

When ASC pin is high the flag reports '1', otherwise

is '0'.

See details in

Section 7.12 on

page 36

Table 52. STATUS3 register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DT_ERR

SPI_ERR

REGERRL

OVLOD

UVLOD

Default(1)

Reset

1. The default is forced at the device power-up, when the registers are reset all the flags are forced low (no failures).

STGAP1ASTR датащи(PDF) 62 Page - STMicroelectronics

STGAP1ASTR датащи(HTML) 62 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

датащи скачать

ссылки URL