SST25VF080B datasheet(15/32 Pages) MICROCHIP

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DS20005045C-page 15

SST25VF080B

4.4.11

WRITE-ENABLE (WREN)

The Write-Enable (WREN) instruction sets the Write-

Enable-Latch bit in the Status Register to 1 allowing

Write operations to occur. The WREN instruction must

be executed prior to any Write (Program/Erase) opera-

tion. The WREN instruction may also be used to allow

execution of the Write-Status-Register (WRSR) instruc-

tion; however, the Write-Enable-Latch bit in the Status

WRSR instruction. CE# must be driven high before the

WREN instruction is executed.

FIGURE 4-15:

WRITE ENABLE (WREN) SEQUENCE

4.4.12

WRITE-DISABLE (WRDI)

The Write-Disable (WRDI) instruction resets the Write-

Enable-Latch bit and AAI bit to 0 disabling any new

Write operations from occurring. The WRDI instruction

will not terminate any programming operation in prog-

ress. Any program operation in progress may continue

up to TBP after executing the WRDI instruction. CE#

must be driven high before the WRDI instruction is exe-

cuted.

FIGURE 4-16:

WRITE DISABLE (WRDI) SEQUENCE

4.4.13

ENABLE-WRITE-STATUS-

The Enable-Write-Status-Register (EWSR) instruction

arms the Write-Status-Register (WRSR) instruction

and opens the status register for alteration. The Write-

Status-Register instruction must be executed immedi-

ately after the execution of the Enable-Write-Status-

instruction.

This

two-step

instruction

sequence of the EWSR instruction followed by the

WRSR instruction works like SDP (software data pro-

tection) command structure which prevents any acci-

dental alteration of the status register values. CE# must

be driven low before the EWSR instruction is entered

and must be driven high before the EWSR instruction

is executed.

CE#

SCK

01 2 3 4 5 6 7

HIGH IMPEDANCE

MODE 0

MODE 3

1296 WREN.0

MSB

CE#

SCK

01 2 3 4 5 6 7

HIGH IMPEDANCE

MODE 0

MODE 3

1296 WRDI.0

MSB

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