SST25WF080B datasheet(15/39 Pages) MICROCHIP

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DS20005164C-page 15

SST25WF080B

5.8

Chip-Erase

The Chip-Erase instruction clears all bits in the device

to FFH. A Chip-Erase instruction is ignored if any of the

memory area is protected. Prior to any Write operation,

the Write-Enable (WREN) instruction must be executed.

CE# must remain active low for the duration of the

Chip-Erase instruction sequence. Initiate the Chip-

Erase instruction by executing an 8-bit command, 60H

or C7H. CE# must be driven high before the instruction is

executed. Poll the BUSY bit in the Software Status reg-

ister, or wait TSCE, for the completion of the internal

self-timed Chip-Erase cycle. See Figure 5-8 for the

Chip-Erase sequence and Figure 6-10 for the flow

chart.

FIGURE 5-8:

CHIP-ERASE SEQUENCE

5.9

Read-Status-Register (RDSR)

The Read-Status-Register (RDSR) instruction, 05H,

allows reading of the status register. The status register

may be read at any time even during a Write (Program/

Erase) operation. When a Write operation is in prog-

ress, the Busy bit may be checked before sending any

new commands to assure that the new commands are

properly received by the device. CE# must be driven

low before the RDSR instruction is entered and remain

low until the status data is read. Read-Status-Register

is continuous with ongoing clock cycles until it is termi-

nated by a low to high transition of the CE#. See Figure

5-9 for the RDSR instruction sequence.

FIGURE 5-9:

READ-STATUS-REGISTER (RDSR) SEQUENCE

CE#

SCK

01 2 3 4 5 6 7

60 or C7

HIGH IMPEDANCE

MODE 0

MODE 3

25164 F16.0

MSB

101112

25164 F17.0

MODE 3

SCK

CE#

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0

HIGH IMPEDANCE

Status

MSB

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