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SST25WF080B датащи(PDF) 14 Page - Microchip Technology

номер детали SST25WF080B
подробное описание детали  8 Mbit 1.8V SPI Serial Flash
PDF  39 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

SST25WF080B датащи(HTML) 14 Page - Microchip Technology

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SST25WF080B
DS20005164C-page 14
 2014 Microchip Technology Inc.
5.6
Sector-Erase
The Sector-Erase instruction clears all bits in the
selected 4 KByte sector to FFH. A Sector-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must
remain active low for the duration of any command
sequence. The Sector-Erase instruction is initiated by
executing an 8-bit command, 20H or D7H, followed by
address bits [A23-A0]. Address bits [AMS-A12]
(AMS = Most Significant address) are used to deter-
mine the sector address (SAX), remaining address bits
can be VIL or VIH. CE# must be driven high before the
instruction is executed. Poll the BUSY bit in the Soft-
ware Status register, or wait TSE, for the completion of
the internal self-timed Sector-Erase cycle. See Figure
5-6 for the Sector-Erase sequence and Figure 6-9 for
the flow chart.
FIGURE 5-6:
SECTOR-ERASE SEQUENCE
5.7
64-KByte Block-Erase
The 64-KByte Block-Erase instruction clears all bits in
the selected 64 KByte block to FFH. Applying this
instruction to a protected memory area results in the
instruction being ignored. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of any com-
mand sequence.
Initiate the 64-Byte Block-Erase instruction by execut-
ing an 8-bit command, D8H, followed by address bits
[A23-A0]. Address bits [AMS-A16] (AMS = Most Signifi-
cant Address) determine the block address (BAX),
remaining address bits can be VIL or VIH. CE# must be
driven high before executing the instruction. Poll the Busy bit
in the software status register or wait TBE for the com-
pletion of the internal self-timed Block-Erase cycle. See
Figure 5-7 for the 64-KByte Block-Erase sequences
and Figure 6-9 for the flow chart.
FIGURE 5-7:
64-KBYTE BLOCK-ERASE SEQUENCE
CE#
SO
SI
SCK
ADD.
01 2 3 4 5 6 7 8
ADD.
ADD.
20 or D7
HIGH IMPEDANCE
15 16
23 24
31
MODE 0
MODE 3
25164 F13.0
MSB
MSB
CE#
SO
SI
SCK
ADDR
01 2 3 4 5 6 7 8
ADDR
ADDR
D8
HIGH IMPEDANCE
15 16
23 24
31
MODE 0
MODE 3
25164 F15.0
MSB
MSB



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