SST39VF401C datasheet(9/38 Pages) MICROCHIP

9 / 38 page

DS20005053B

04/14

4 Mbit (x16) Multi-Purpose Flash Plus

SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C

Data Sheet

Ready/Busy# (RY/BY#)

The devices include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that

indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain out-

put, it allows several devices to be tied in parallel to VDD via an external pull-up resistor. After the rising

edge of the final WE# pulse in the command sequence, the RY/BY# status is valid.

When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is in progress.

When RY/BY# is high (Ready), the devices may be read or left in standby mode.

Data# Polling (DQ7)

When the SST39VF401C/402C and SST39LF401C/402C are in the internal Program operation, any

attempt to read DQ7 will produce the complement of the true data. Once the Program operation is

completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately follow-

ing the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on

the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal

Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is com-

pleted, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#)

pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the ris-

ing edge of sixth WE# (or CE#) pulse. See Figure 9 for Data# Polling timing diagram and Figure 23 for

a flowchart.

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce

alternating ‘1’s and ‘0’s, i.e., toggling between 1 and 0. When the internal Program or Erase operation

is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector-

, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse.

DQ6 will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector/Block. If Pro-

gram operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle.

An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check

whether a particular sector is being actively erased or erase-suspended. Table 3 shows detailed status

bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of

Write operation. See Figure 10 for Toggle Bit timing diagram and Figure 23 for a flowchart.

Note: DQ7 and DQ2 require a valid address when reading status information.

Table 3: Write Operation Status

Status

DQ7

DQ6

DQ2

RY/BY#

Normal Operation

Standard Program

DQ7#

Toggle

No Toggle

Standard Erase

Toggle

Erase-Suspend

Mode

Read from Erase-Sus-

pended Sector/Block

Toggle

Read from Non-Erase-

Suspended Sector/Block

Data

Program

DQ7#

Toggle

N/A

T3.0 25053

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