SST25WF512 datasheet(13/36 Pages) MICROCHIP

13 / 36 page

DS20005016C

11/14

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash

SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040

EOL Data Sheet

Read (20 MHz)

The Read instruction, 03H, supports up to 20 MHz Read. The device outputs a data stream starting

from the specified address location. The data stream is continuous through all addresses until termi-

nated by a low-to-high transition on CE#. The internal address pointer automatically increments until

the highest memory address is reached. Once the highest memory address is reached, the address

pointer automatically increments to the beginning (wrap-around) of the address space. For example,

for 2 Mbit density, once the data from the address location 3FFFFH is read, the next output is from

address location 000000H. The Read instruction is initiated by executing an 8-bit command, 03H, fol-

lowed by address bits A23-A0. CE# must remain active low for the duration of the Read cycle. See Fig-

ure 6 for the Read sequence.

Figure 6: Read Sequence

1. One bus cycle is eight clock periods.

2. Address bits above the most significant bit of each density can be VIL or VIH.

3. 4 KByte Sector-Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.

4. 32 KByte Block-Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.

5. 64 KByte Block-Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH.

6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of

data to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be

programmed into the

initial address [A23-A1] with A0 =1.

7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.

8. Either EWSR or WREN followed by WRSR will write to the Status register. The EWSR-WRSR sequence provides back-

ward compatibility to the SST25VF/LF series. The WREN-WRSR sequence is recommended for new designs.

9. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufac-

turer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#.

1328 Fx6.0

CE#

SCK

ADD.

01 2 3 4 5 6 7 8

ADD.

HIGH IMPEDANCE

15 16

23 24

31 32

39 40

55 56

63 64

N+2

N+3

N+4

N+1

DOUT

MSB

MODE 0

MODE 3

DOUT

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