©2014 Silicon Storage Technology, Inc.

DS20005016C

11/14

21

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash

SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040

EOL Data Sheet

Write-Disable (WRDI)

The Write-Disable (WRDI) instruction, 04H, resets the Write-Enable-Latch bit and AAI to 0 disabling

any new Write operations from occurring. The WRDI instruction will not terminate any programming

WRDI instruction. CE# must be driven high before the WRDI instruction is executed. See Figure 19 for

the WRDI instruction sequence.

Figure 19:Write Disable (WRDI) Sequence

Enable-Write-Status-Register (EWSR)

The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR)

instruction and opens the status register for alteration. The Write-Status-Register instruction must be

executed immediately after the execution of the Enable-Write-Status-Register instruction. This two-

step instruction sequence of the EWSR instruction followed by the WRSR instruction works like SDP

(software data protection) command structure which prevents any accidental alteration of the status

register values. CE# must be driven low before the EWSR instruction is entered and must be driven

high before the EWSR instruction is executed. See Figure 20 for EWSR instruction followed by WRSR

instruction.

Write-Status-Register (WRSR)

The Write-Status-Register instruction writes new values to the BP1, BP0, and BPL bits of the status

register. CE# must be driven low before the command sequence of the WRSR instruction is entered

and driven high before the WRSR instruction is executed. See Figure 20 for EWSR or WREN and

WRSR instruction sequences.

Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to

‘1’. When the WP# is low, the BPL bit can only be set from ‘0’ to ‘1’ to lock-down the status register, but

cannot be reset from ‘1’ to ‘0’. When WP# is high, the lock-down function of the BPL bit is disabled and

the BPL, BP0, and BP1 bits in the status register can all be changed. As long as BPL bit is set to ‘0’ or

instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a sin-

gle WRSR instruction can set the BPL bit to ‘1’ to lock down the status register as well as altering the

BP0, and BP1 bits at the same time. See Table 3 for a summary description of WP# and BPL func-

CE#

SO

SI

SCK

01 2 3 4 5 6 7

04

HIGH IMPEDANCE

MODE 0

MODE 3

1328 Fx19.0

MSB