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SST25WF512 датащи(PDF) 9 Page - Microchip Technology |
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SST25WF512 датащи(HTML) 9 Page - Microchip Technology |
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9 / 36 page ![]() ©2014 Silicon Storage Technology, Inc. DS20005016C 11/14 9 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 EOL Data Sheet Auto Address Increment (AAI) The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI programming mode or Byte-Program mode. The default at power up is Byte-Program mode. Block-Protection (BP2, BP1, BP0) The Block-Protection (BP1, BP0) bits define the size of the memory area to be software protected against any memory Write (Program or Erase) operation, see Tables 5-7. The Write-Status-Register (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-Pro- tect-Lock (BPL) bit is ‘0’. Chip-Erase can only be executed if Block-Protection bits are all ‘0’. After power-up, BP2, BP1, and BP0 are set to defaults. See Table 4 for defaults at power-up. Block Protection Lock-Down (BPL) When the WP# pin is driven low (VIL), it enables the Block-Protection-Lock-Down (BPL) bit. When BPL is set to ‘1’, it prevents any further alteration of the BPL, BP1, and BP0 bits. When the WP# pin is driven high (VIH), the BPL bit has no effect and its value is ‘Don’t Care’. After power-up, the BPL bit is reset to ‘0’. Table 5: Software Status Register Block Protection for SST25WF512 Protection Level Status Register Bit Protected Memory Address BP11 1. Default at power-up for BP1 and BP0 is ‘11’. BP0 512 Kbit None 0 0 None 1 (Upper Quarter Memory) 0 1 00C000H-00FFFFH 2 (Upper Half Memory) 1 0 008000H-00FFFFH 3 (Full Memory) 1 1 000000H-00FFFFH T5.1 20005016 Table 6: Software Status Register Block Protection for SST25WF010 Protection Level Status Register Bit Protected Memory Address BP11 1. Default at power-up for BP1 and BP0 is ‘11’. BP0 1 Mbit None 0 0 None 1 (Upper Quarter Memory) 0 1 018000H-01FFFFH 2 (Upper Half Memory) 1 0 010000H-01FFFFH 3 (Full Memory) 1 1 000000H-01FFFFH T6.0 20005016 Table 7: Software Status Register Block Protection for SST25WF020 Protection Level Status Register Bit Protected Memory Address BP11 1. Default at power-up for BP1 and BP0 is ‘11’. BP0 2 Mbit None 0 0 None 1 (Upper Quarter Memory) 0 1 030000H-03FFFFH 2 (Upper Half Memory) 1 0 020000H-03FFFFH 3 (Full Memory) 1 1 000000H-03FFFFH T7.0 20005016 |
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