HTS221 datasheet(24/33 Pages) STMICROELECTRONICS

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HTS221

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DocID026333 Rev 4

7.5

CTRL_REG3 (22h)

Control register 3

Control register for data ready output signal

The DRDY_EN bit enables the DRDY signal on pin 3. Normally inactive, the DRDY output

signal becomes active on new data available: logical OR of the bits STATUS_REG[1] and

STATUS_REG[0] for humidity and temperature, respectively. The DRDY signal returns

inactive after both HUMIDITY_OUT_H and TEMP_OUT_H registers are read.

7.6

STATUS_REG (27h)

Status register

Status register; the content of this register is updated every one-shot reading, and after

completion of every ODR cycle, regardless of the BDU value in CTRL_REG1.

76543210

DRDY_H_L

PP_OD

Reserved

DRDY

Reserved

[7]

DRDY_H_L: Data Ready output signal active high, low

(0: active high - default;1: active low)

[6]

PP_OD: Push-pull / Open Drain selection on pin 3 (DRDY)

(0: push-pull - default; 1: open drain)

[5:3]

Reserved

[2]

DRDY_EN: Data Ready enable

(0: Data Ready disabled - default;1: Data Ready signal available on pin 3)

[1:0]

Reserved

76543210

Reserved

H_DA

T_DA

[7:2]

Reserved

[1]

H_DA: Humidity data available.

(0: new data for humidity is not yet available; 1: new data for humidity is available)

[0]

T_DA: Temperature data available.

(0: new data for temperature is not yet available; 1: new data for temperature is available)

H_DA is set to 1 whenever a new humidity sample is available. H_DA is cleared anytime

HUMIDITY_OUT_H (29h) register is read.

T_DA is set to 1 whenever a new temperature sample is available. T_DA is cleared

anytime TEMP_OUT_H (2Bh) register is read.

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