Digital interfaces

HTS221

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DocID026333 Rev 4

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number

of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit

(MSB) first. If a receiver can’t receive another complete byte of data until it has performed

some other functions, it can hold the clock line, SCL LOW to force the transmitter into a wait

state. Data transfer only continues when the receiver is ready for another byte and releases

the data line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to

receive because it is performing some real-time function) the data line must be kept HIGH

by the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA

line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be

terminated by the generation of a STOP (SP) condition.

In order to read multiple bytes incrementing the register address, it is necessary to assert

the most significant bit of the sub-address field. In other words, SUB(7) must be equal to 1

while SUB(6-0) represents the address of the first register to be read.

In the presented communication format MAK is master acknowledge and NMAK is no

master acknowledge.

I²C high speed HS-mode devices can transfer information at bit rates of up to 3.4 Mbit/s, yet

they remain fully downward compatible with fast or standard-mode (F/S-mode) devices for

bi-directional communication in a mixed-speed bus system. With the exception that

arbitration and clock synchronization is not performed during the HS-mode transfer, the

same serial bus protocol and data format is maintained as with the F/S-mode system.

HS-mode can only begin after the following conditions (all of which are in F/S-mode):

1.

START condition (S)

2.

8-bit master code (00001XXX)

3.

not-acknowledge bit (A)

This master code has two main functions:

It allows arbitration and synchronization between competing masters at F/S-mode speeds,

resulting in one winning master.

It indicates the beginning of an HS-mode transfer. HS-mode master codes are reserved

8-bit codes, which are not used for slave addressing or other purposes.

The master code indicates to other devices that an HS-mode transfer is to begin and the

connected devices must meet the HS-mode specification. As no device is allowed to

acknowledge the master code, the master code is followed by a not-acknowledge (A). After

the not-acknowledge bit (A), and the SCLH line has been pulled up to a HIGH level, the

Table 13. Transfer when master is receiving (reading) one byte of data from slave

Master

ST

SAD + W

SUB

SR

SAD + R

NMAK

SP

Slave

SAK

SAK

SAK

DATA

Table 14. Transfer when master is receiving (reading) multiple bytes of data from

slave

Master

ST

SAD+W

SUB

SR

SAD+R

MAK

MAK

NMAK

SP

Slave

SAK

SAK

SAK

DATA

DATA

DATA